Senior RTL/Synthesis Engineer

Job role: Senior RTL/Synthesis Engineer
Location: Bay Area,CA


we need strong designer in following 2 requirements
Strong in RTL/Synthesis, Fusion-Compiler, Script wrapper handling around tools using Python/Perl/TCL
Strong in RTL/Synthesis/CDC/STA/Constraints
JD:
What You'll Be Doing:
• 7+ years of related technical engineering experience
• 5+ years of experience applying digital design principles in SoC and/or IP development.
• Proficient in Verilog/System Verilog coding constructs and Synthesis.
• Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power
static checkers, linting)
• Experience with high speed PCIe designs and protocols.
• Experience with Industry standard interface protocols such as AXI, APB, etc.
• Experience with ARM Fabric IPs.
• Experience with IPXACT.
• Understanding of Computer Architecture fundamentals.
• Ability to write scripts using Python, Tcl, Perl etc.
• Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design
Compiler, Genus.
What We Are Looking For:
• BS or MS in Electrical Engineering (or equivalent)
• • Proficiency with UPF (Low power intent)
• Proficiency in clock crossing techniques.
• Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.NoC tool
Education:
• Bachelor’s / Masters



Thank you.

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