T
Senior RTL Design Engineer
Accepting applicationsTessolve · Bangalore Urban, Karnataka, India
Full-Time Mid_senior ASICCadenceDFTRISC-VRTL
Estimated market salary
₹21-38 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
India
JOB DESCRIPTION
Title/Position: Senior RTL Design Engineer
Location: Bangalore, Hyderabad
Experience: 5 to 15 Years
Mail ID- Mallika.dhamotharapandiyan@tessolve.com
Type: Fulltime
Key Skills and Responsibilities:
Microarchitecture, Module design and simulation
Digital design, implementation and integration – RTL Coding, Lint, CDC, and Synthesis.
Develop design constraints and coordinate to debug both functional and DFT test issues.
Synthesis and P&R constraint generation, including clock tree specification
Scan insertion and pattern generation
Support IP/Design Verification/Firmware/Software System to provide the necessary support for timely closure of assigned blocks design and implementation issues.
Job Requirements
Digital design knowledge:
Verilog coding
Register file design
Serial interfaces
Interconnect fabrics
State machine architecture
Clock domain crossing
Scan and self-test
Synthesis, Linting, STA
Automation scripting and design flows
Verification, including System Verilog knowledge
Low power design, Power intent specification and validation methodology.
Battery management and RISC-V based Subsystems/SOCs.
Knowledge of TFM (Tools, Flows and Methodologies) flows: Simulation, Lint, CDC/RDC and power intent checks UPF.
Familiarity with Cadence, Synopsis design tools
Ability to work as part of a team and with low levels of supervision
About us:
Tessolve Semiconductors, a venture of Hero Electronix, is a Design and Test Engineering Service
Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless,
Automotive and Embedded Solutions.
Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, spec to the product. With 2500+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. We have a global presence with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, China, UK, Japan, Thailand, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose.
Tessolve offers a highly competitive compensation and benefits along with an electric work environment to scale one’s intellect, skills and growth.
Disclaimer:
At Tessolve, we are committed to fostering a workplace that embraces and celebrates diversity in all its forms. We believe that diverse teams drive innovation, creativity, and success. We are dedicated to creating an inclusive environment where all employees, regardless of their race, color, religion, gender, gender identity or expression, sexual orientation, national origin, genetics, disability, age, or veteran status, feel valued and respected. We believe in fair and equitable treatment for all employees and aim to eliminate any biases or barriers that may hinder personal or professional growth.
Show more Show less
Title/Position: Senior RTL Design Engineer
Location: Bangalore, Hyderabad
Experience: 5 to 15 Years
Mail ID- Mallika.dhamotharapandiyan@tessolve.com
Type: Fulltime
Key Skills and Responsibilities:
Microarchitecture, Module design and simulation
Digital design, implementation and integration – RTL Coding, Lint, CDC, and Synthesis.
Develop design constraints and coordinate to debug both functional and DFT test issues.
Synthesis and P&R constraint generation, including clock tree specification
Scan insertion and pattern generation
Support IP/Design Verification/Firmware/Software System to provide the necessary support for timely closure of assigned blocks design and implementation issues.
Job Requirements
Digital design knowledge:
Verilog coding
Register file design
Serial interfaces
Interconnect fabrics
State machine architecture
Clock domain crossing
Scan and self-test
Synthesis, Linting, STA
Automation scripting and design flows
Verification, including System Verilog knowledge
Low power design, Power intent specification and validation methodology.
Battery management and RISC-V based Subsystems/SOCs.
Knowledge of TFM (Tools, Flows and Methodologies) flows: Simulation, Lint, CDC/RDC and power intent checks UPF.
Familiarity with Cadence, Synopsis design tools
Ability to work as part of a team and with low levels of supervision
About us:
Tessolve Semiconductors, a venture of Hero Electronix, is a Design and Test Engineering Service
Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless,
Automotive and Embedded Solutions.
Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, spec to the product. With 2500+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. We have a global presence with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, China, UK, Japan, Thailand, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose.
Tessolve offers a highly competitive compensation and benefits along with an electric work environment to scale one’s intellect, skills and growth.
Disclaimer:
At Tessolve, we are committed to fostering a workplace that embraces and celebrates diversity in all its forms. We believe that diverse teams drive innovation, creativity, and success. We are dedicated to creating an inclusive environment where all employees, regardless of their race, color, religion, gender, gender identity or expression, sexual orientation, national origin, genetics, disability, age, or veteran status, feel valued and respected. We believe in fair and equitable treatment for all employees and aim to eliminate any biases or barriers that may hinder personal or professional growth.
Show more Show less
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