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Senior RTL Design Engineer
Accepting applicationsLumicity · Texas, United States
Full-Time Mid_senior RTLSystemVerilogVerilogaiate
Posted
27 Apr
Category
Design
Experience
Mid_senior
Country
United States
Responsibilities
Design and implement RTL for a next-generation high-performance processing platform.
Contribute to the development of advanced digital architectures, including scheduling mechanisms, interconnect systems, and data movement engines.
Develop and optimize components with a focus on performance and power efficiency, such as datapaths, control logic, memory subsystems, and on-chip interconnects.
Work closely with architecture and verification teams to define microarchitecture and validate functionality.
Support timing closure in collaboration with synthesis and physical design teams.
Participate in design reviews and help improve RTL development practices and methodologies.
Requirements
Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
4+ years of experience in RTL design and microarchitecture development.
Strong understanding of computer architecture concepts (e.g., pipelining, caching, memory hierarchy).
Experience with one or more of the following areas: interconnect design, data movement engines, memory subsystems, or control/datapath logic.
Proficiency in Verilog or SystemVerilog and familiarity with standard RTL design practices.
Understanding of timing constraints and physical design considerations.
Experience with simulation, synthesis, linting, and timing analysis tools.
Strong analytical, problem-solving, and communication skills; ability to collaborate across teams.
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Design and implement RTL for a next-generation high-performance processing platform.
Contribute to the development of advanced digital architectures, including scheduling mechanisms, interconnect systems, and data movement engines.
Develop and optimize components with a focus on performance and power efficiency, such as datapaths, control logic, memory subsystems, and on-chip interconnects.
Work closely with architecture and verification teams to define microarchitecture and validate functionality.
Support timing closure in collaboration with synthesis and physical design teams.
Participate in design reviews and help improve RTL development practices and methodologies.
Requirements
Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
4+ years of experience in RTL design and microarchitecture development.
Strong understanding of computer architecture concepts (e.g., pipelining, caching, memory hierarchy).
Experience with one or more of the following areas: interconnect design, data movement engines, memory subsystems, or control/datapath logic.
Proficiency in Verilog or SystemVerilog and familiarity with standard RTL design practices.
Understanding of timing constraints and physical design considerations.
Experience with simulation, synthesis, linting, and timing analysis tools.
Strong analytical, problem-solving, and communication skills; ability to collaborate across teams.
Show more Show less