Senior RTL Design Engineer

Job Title: Senior RTL Design Engineer
Location: Austin, TX (Onsite)
Experience: 8+ Years
Visa- Any Visa will work
Rate: $60/Hour
Interview : Virtual Interview/In person
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
8–10+ years of overall experience in ASIC/SoC Digital Design and RTL development.
Minimum 5+ years of hands-on experience in Verilog RTL design and development.
Strong understanding of digital design fundamentals, RTL design methodologies, and synthesis flows.
Proven experience with EDA tools for:
Clock Domain Crossing (CDC) analysis
Static Timing Analysis (STA)
Logic synthesis
Strong knowledge of AMBA AXI protocols and related system architectures.
Experience working with Network-on-Chip (NoC) design and integration.
Excellent debugging, analytical, and problem-solving skills.
Strong written and verbal communication skills with the ability to interact directly with customers.

Preferred Qualifications
Experience working in customer-facing engineering roles.
Familiarity with complete ASIC/SoC development flows.
Ability to work independently and manage multiple priorities in a fast-paced environment.
Experience collaborating with globally distributed teams.

Interested candidates can share resume with saloni.dhawade@leanitcorp.com
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