JV
Senior RTL Design Engineer
Accepting applicationsJobs via Dice · Austin, TX
Full-Time Principal ASICRTLSoCVerilog
Posted
6d ago
Category
Design
Experience
Principal
Country
United States
Dice is the leading career destination for tech experts at every stage of their careers. Our client, EXPRESSBILLPAY LLC, is seeking the following. Apply via Dice today!
Job Title: Senior RTL Design Engineer
Location: Austin, TX (Onsite)
Visa- Any Visa will work
Interview : Virtual Interview/In person
Key Responsibilities
Design, develop, and implement RTL solutions for complex digital and SoC designs.
Analyze design specifications and translate them into high-quality RTL implementations.
Perform synthesis, timing analysis, and design optimization to meet performance, power, and area goals.
Conduct Clock Domain Crossing (CDC) analysis and Static Timing Analysis (STA) to ensure robust and reliable designs.
Work with AMBA AXI-based interconnects and Network-on-Chip (NoC) architectures.
Collaborate with verification, physical design, and system teams throughout the development cycle.
Debug and resolve RTL, synthesis, timing, and integration issues.
Interface directly with customers to understand requirements, provide technical guidance, and address design challenges.
Ensure customer satisfaction through effective communication and timely delivery of project milestones.
Prepare and present daily and weekly progress reports to customers and internal stakeholders.
Support project planning, risk assessment, and technical reviews.
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
8–10+ years of overall experience in ASIC/SoC Digital Design and RTL development.
Minimum 5+ years of hands-on experience in Verilog RTL design and development.
Strong understanding of digital design fundamentals, RTL design methodologies, and synthesis flows.
Proven experience with EDA tools for:
Clock Domain Crossing (CDC) analysis
Static Timing Analysis (STA)
Logic synthesis
Strong knowledge of AMBA AXI protocols and related system architectures.
Experience working with Network-on-Chip (NoC) design and integration.
Excellent debugging, analytical, and problem-solving skills.
Strong written and verbal communication skills with the ability to interact directly with customers.
Preferred Qualifications
Experience working in customer-facing engineering roles.
Familiarity with complete ASIC/SoC development flows.
Ability to work independently and manage multiple priorities in a fast-paced environment.
Experience collaborating with globally distributed teams.
Interested Candidates please share resume on (dot) com
Show more Show less
Job Title: Senior RTL Design Engineer
Location: Austin, TX (Onsite)
Visa- Any Visa will work
Interview : Virtual Interview/In person
Key Responsibilities
Design, develop, and implement RTL solutions for complex digital and SoC designs.
Analyze design specifications and translate them into high-quality RTL implementations.
Perform synthesis, timing analysis, and design optimization to meet performance, power, and area goals.
Conduct Clock Domain Crossing (CDC) analysis and Static Timing Analysis (STA) to ensure robust and reliable designs.
Work with AMBA AXI-based interconnects and Network-on-Chip (NoC) architectures.
Collaborate with verification, physical design, and system teams throughout the development cycle.
Debug and resolve RTL, synthesis, timing, and integration issues.
Interface directly with customers to understand requirements, provide technical guidance, and address design challenges.
Ensure customer satisfaction through effective communication and timely delivery of project milestones.
Prepare and present daily and weekly progress reports to customers and internal stakeholders.
Support project planning, risk assessment, and technical reviews.
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
8–10+ years of overall experience in ASIC/SoC Digital Design and RTL development.
Minimum 5+ years of hands-on experience in Verilog RTL design and development.
Strong understanding of digital design fundamentals, RTL design methodologies, and synthesis flows.
Proven experience with EDA tools for:
Clock Domain Crossing (CDC) analysis
Static Timing Analysis (STA)
Logic synthesis
Strong knowledge of AMBA AXI protocols and related system architectures.
Experience working with Network-on-Chip (NoC) design and integration.
Excellent debugging, analytical, and problem-solving skills.
Strong written and verbal communication skills with the ability to interact directly with customers.
Preferred Qualifications
Experience working in customer-facing engineering roles.
Familiarity with complete ASIC/SoC development flows.
Ability to work independently and manage multiple priorities in a fast-paced environment.
Experience collaborating with globally distributed teams.
Interested Candidates please share resume on (dot) com
Show more Show less
Similar Jobs
M
MTS, Analog Design Engineering
Micron · Boise, United States, North America
M
Senior Engineer, STPG PE (FDV-Verilog)
Micron · Singapore, Singapore, Asia
M
Digital IC Design Engineer - Early Career
Marvell · Westborough, United States, North America
M
Staff Firmware/Software Engineer- Embedded SoC/Microcontroller/DSP/SERDES/AEC/Microled/ODSP/PHY/AI Connectivity
Marvell · Santa Clara, United States, North America