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Senior RTL Design Engineer
Accepting applicationsGoogle · Mountain View, CA
Full-Time Mid_senior AIASICDFTFPGAPerl
Posted
4d ago
Category
Design
Experience
Mid_senior
Country
United States
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience with IP Development or Integration.
Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language).
Experience with a scripting language (e.g., Python or Perl).
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with ASIC design methodologies for clock domain checks, reset checks, and low power design.
Knowledge of one of these areas: processor cores, buses/fabric/NoC, debug/trace, interrupts, clocks/reset.
Knowledge of high-performance and low-power design techniques.
Knowledge of ASIC Verification, DFT, synthesis, STA, or physical design.
Knowledge of FPGA and emulation platforms.
About The Job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits
Responsibilities
Learn more about benefits at Google .
Define the detailed microarchitecture specifications for silicon subsystems and small to medium-sized intellectual property blocks to meet performance, area, and power requirements.
Integrate internal and external intellectual property (IP) blocks seamlessly into complex silicon designs and multi-component subsystems.
Execute production-grade RTL coding, debug intricate function and performance simulation issues, and conduct standard lint, clock domain crossing, formal verification, and unified power format checks.
Partner closely with validation teams during test plan formulation and coverage analysis for comprehensive subsystem and chip-level design verification.
Drive technical alignment across multi-disciplinary and multi-site engineering groups to resolve architectural issues and ensure successful product delivery.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
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Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience with IP Development or Integration.
Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language).
Experience with a scripting language (e.g., Python or Perl).
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with ASIC design methodologies for clock domain checks, reset checks, and low power design.
Knowledge of one of these areas: processor cores, buses/fabric/NoC, debug/trace, interrupts, clocks/reset.
Knowledge of high-performance and low-power design techniques.
Knowledge of ASIC Verification, DFT, synthesis, STA, or physical design.
Knowledge of FPGA and emulation platforms.
About The Job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits
Responsibilities
Learn more about benefits at Google .
Define the detailed microarchitecture specifications for silicon subsystems and small to medium-sized intellectual property blocks to meet performance, area, and power requirements.
Integrate internal and external intellectual property (IP) blocks seamlessly into complex silicon designs and multi-component subsystems.
Execute production-grade RTL coding, debug intricate function and performance simulation issues, and conduct standard lint, clock domain crossing, formal verification, and unified power format checks.
Partner closely with validation teams during test plan formulation and coverage analysis for comprehensive subsystem and chip-level design verification.
Drive technical alignment across multi-disciplinary and multi-site engineering groups to resolve architectural issues and ensure successful product delivery.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Show more Show less