Senior RTL Design

🚀 Hiring: RTL Design Engineer – PCIe / CXL (5+ Years Experience)
📍 Location: Bangalore, India
💼 Experience: 5+ Years

Job Description
We are looking for an experienced RTL Design Engineer with strong expertise in PCIe and/or CXL protocol-based IP design. The ideal candidate will have hands-on experience in ASIC/SoC development, microarchitecture, RTL coding, and integration of high-speed interfaces.

Key Responsibilities
Design and develop RTL for PCIe and/or CXL-based IPs and subsystems.
Create microarchitecture specifications from system requirements.
Develop high-quality RTL using Verilog/SystemVerilog.
Perform block-level design, integration, and debugging.
Collaborate with verification, architecture, DFT, and physical design teams.
Support synthesis, lint, CDC, and timing closure activities.
Participate in design reviews and technical discussions.

Required Skills
5+ years of experience in RTL Design/ASIC Design.
Strong expertise in PCIe (Gen3/Gen4/Gen5) and/or CXL protocols.
Proficient in Verilog/SystemVerilog coding.
Good understanding of SoC architecture and high-speed interfaces.
Experience with Lint, CDC, Synthesis, and STA concepts.
Familiarity with AMBA protocols such as AXI/APB.
Strong debugging and problem-solving skills.

Interested candidates, Kindly share with me your updated profile to naveen.a@modernchipsolutions.com
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