MT
Senior Principal STA Engineer
Accepting applicationsMulya Technologies · Greater Bengaluru Area
Full-Time Mid_senior AIASICDFTEthernetMentor
Estimated market salary
₹20-36 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
19h ago
Category
Design
Experience
Mid_senior
Country
India
Principal Engineer, Static Timing Analysis
Top30 Semiconductor Organization in the world
Bangalore
We are hiring a Principal Engineer, Static Timing Analysis to own top-level timing closure and signoff for our next-generation connectivity silicon powering rack-scale AI infrastructure. In this role, you'll drive full-chip STA strategy across advanced process nodes, partner with physical design, RTL, DFT, and CAD teams, and ensure first-pass timing success on some of the most complex SoCs in the industry.
This is a high-impact technical leadership role at a hyper-growth company purpose-built for AI connectivity. Your work directly enables the PCIe, CXL, UALink, and Ethernet platforms that hyperscalers depend on — and you'll have the ownership, influence, and tooling to do the best work of your career.
Key Responsibilities
Full-Chip STA Signoff & Timing Closure
Own end-to-end top-level STA signoff across multiple modes, corners, and operating conditions (MMMC) for complex AI connectivity SoCs
Drive timing convergence on advanced process nodes (5nm/4nm/3nm and below) from early floorplan through tapeout
Analyze and resolve setup, hold, recovery/removal, and clock-domain crossing (CDC) timing violations at the chip level
Methodology & Flow Development
Define and evolve STA methodology, constraints (SDC) strategy, and signoff criteria across the organization
Develop and automate flows using PrimeTime, PrimeTime SI, and related signoff tools for crosstalk, noise, and IR-aware timing
Establish best practices for hierarchical STA, ETM/IPXACT model generation, and budgeting across blocks
Cross-Functional Technical Leadership
Partner with Physical Design, RTL, DFT, CAD, and Package teams to drive timing-aware design decisions from architecture through tapeout
Review and sign off on block-level timing handoffs, ensuring consistency between block and top-level closure
Collaborate with low-power design teams on UPF/CPF, multi-voltage, and clock-gating timing implications
Mentorship & Technical Strategy
Mentor STA engineers and review timing reports, ECOs, and signoff collateral
Drive root-cause analysis of silicon timing issues and feed learnings back into methodology
Influence tool selection, EDA vendor engagements, and STA roadmap for future products
Basic Qualifications
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field
14+ years of hands-on experience in Static Timing Analysis on complex ASIC/SoC designs
Proven track record of full-chip top-level STA signoff on at least one tapeout at advanced nodes (7nm or below)
Deep expertise with PrimeTime, PrimeTime SI, and SDC constraint development
Strong understanding of clocking architectures, CDC, OCV/AOCV/POCV, crosstalk, and IR-aware timing
Proficiency in scripting (Tcl, Python, Perl) for STA flow automation and report analysis
Preferred Qualifications
Experience with high-speed connectivity SoCs (PCIe Gen 6/7, CXL, UALink, or Ethernet)
Familiarity with hierarchical STA, ETM/ILM models, and timing budgeting across large partitions
Experience with low-power signoff (UPF/CPF), multi-voltage domains, and DVFS timing implications
Strong cross-functional collaboration and mentorship skills in a fast-paced product environment
Skills
SoC
PCIe
CXL
UAL (UA Link)
Ethernet
"hiearchial STA"
UPF
CPF
Primetime
SDC
Timing
ECO
Contact:Uday
Mulya Technologies
muday_bhaskar@yahoo.com
Show more Show less
Top30 Semiconductor Organization in the world
Bangalore
We are hiring a Principal Engineer, Static Timing Analysis to own top-level timing closure and signoff for our next-generation connectivity silicon powering rack-scale AI infrastructure. In this role, you'll drive full-chip STA strategy across advanced process nodes, partner with physical design, RTL, DFT, and CAD teams, and ensure first-pass timing success on some of the most complex SoCs in the industry.
This is a high-impact technical leadership role at a hyper-growth company purpose-built for AI connectivity. Your work directly enables the PCIe, CXL, UALink, and Ethernet platforms that hyperscalers depend on — and you'll have the ownership, influence, and tooling to do the best work of your career.
Key Responsibilities
Full-Chip STA Signoff & Timing Closure
Own end-to-end top-level STA signoff across multiple modes, corners, and operating conditions (MMMC) for complex AI connectivity SoCs
Drive timing convergence on advanced process nodes (5nm/4nm/3nm and below) from early floorplan through tapeout
Analyze and resolve setup, hold, recovery/removal, and clock-domain crossing (CDC) timing violations at the chip level
Methodology & Flow Development
Define and evolve STA methodology, constraints (SDC) strategy, and signoff criteria across the organization
Develop and automate flows using PrimeTime, PrimeTime SI, and related signoff tools for crosstalk, noise, and IR-aware timing
Establish best practices for hierarchical STA, ETM/IPXACT model generation, and budgeting across blocks
Cross-Functional Technical Leadership
Partner with Physical Design, RTL, DFT, CAD, and Package teams to drive timing-aware design decisions from architecture through tapeout
Review and sign off on block-level timing handoffs, ensuring consistency between block and top-level closure
Collaborate with low-power design teams on UPF/CPF, multi-voltage, and clock-gating timing implications
Mentorship & Technical Strategy
Mentor STA engineers and review timing reports, ECOs, and signoff collateral
Drive root-cause analysis of silicon timing issues and feed learnings back into methodology
Influence tool selection, EDA vendor engagements, and STA roadmap for future products
Basic Qualifications
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field
14+ years of hands-on experience in Static Timing Analysis on complex ASIC/SoC designs
Proven track record of full-chip top-level STA signoff on at least one tapeout at advanced nodes (7nm or below)
Deep expertise with PrimeTime, PrimeTime SI, and SDC constraint development
Strong understanding of clocking architectures, CDC, OCV/AOCV/POCV, crosstalk, and IR-aware timing
Proficiency in scripting (Tcl, Python, Perl) for STA flow automation and report analysis
Preferred Qualifications
Experience with high-speed connectivity SoCs (PCIe Gen 6/7, CXL, UALink, or Ethernet)
Familiarity with hierarchical STA, ETM/ILM models, and timing budgeting across large partitions
Experience with low-power signoff (UPF/CPF), multi-voltage domains, and DVFS timing implications
Strong cross-functional collaboration and mentorship skills in a fast-paced product environment
Skills
SoC
PCIe
CXL
UAL (UA Link)
Ethernet
"hiearchial STA"
UPF
CPF
Primetime
SDC
Timing
ECO
Contact:Uday
Mulya Technologies
muday_bhaskar@yahoo.com
Show more Show less