MT
Senior Principal Physical Design Engineers
Accepting applicationsMulya Technologies · Greater Hyderabad Area
Full-Time Mid_senior AICadenceCalibreDFTGenus
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
India
Senior Principal Physical Design Engineers
Location: Greater Bengaluru Area (Hybrid)/ Greater Hyderabad
we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.
Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.
our architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.
. Location: Hyderabad/Bangalore
We are actively seeking Physical Design Engineers based in Hyderabad OR Bangalore
Required competences - Experience
15-25 years’ experience in the semiconductor industry, with min. 5 years in a digital Physical Design technical leadership role
Experience on modern semiconductor process technologies including 28nm, 14/16nm, 7nm
Experienced user of EDA tools for design and verification such as, Cadence Genus and Innovus, LEC, Calibre/PVS DRC/LVS, parasitics extraction, EM and IR drop, ESD, etc.
Expertise in Timing Constraints and Static Timing Analysis (STA)
Experience in CPF/UPF technologies and flows is highly desirable
Exposure to flip-chip package technologies and wire bond package technologies
Experience in hierarchical floor planning and implementation
Experience in release management and tape out procedures
Experience in library setup and flow development with focus on cross project reusability
Experience in DFT methodologies and implementation schemesRequired
Competencies – Skills
Required competences - Skills
Good understanding of RTL to GDS implementation flow (synthesis, P&R, LEC, PV)
Self-motivated, with strong sense of ownership and responsibility. Good communicator and team player
Good scripting capabilities (shell, TCL, Python, make) and good understanding of data management (revision control system)
Responsibility and Authority
Responsibility and Authority
As a Physical Design Engineer, you will work closely with the Architecture, RTL, DFT teams to ensure first-time-right high-volume silicon production
Timing constraints improvement and timing constraints validation, signoff Static Timing Analysis and block-level timing closure
Synthesis, block level floor-planning, power grid design, place & route, clock tree synthesis, electromigration / IR-Drop analysis, power/signal integrity analysis, crosstalk analysis, formal equivalence checking and physical verification (DRC / LVS / Antenna)
Participate in developing improvements to scripts/methodologies/flows
Interact closely with the design team to understand requirements and implement solutions as also helping on providing design views for use with digital PD flows (LIB, LEF, DEF, GDS, SPEF, etc.)
Support IP and chip level integration
Support and interact with customers on requirements and IP delivery
Manage workload and schedule and report to internal management team
Education
Bachelors/Masters of Engineering in Electronics and Electrical Engineering/Computer Science (equivalent or higher)
Contact
Uday
muday_bhaskar@yahoo.com
Mulya Technologies
"Mining the Knowledge Community"
Show more Show less
Location: Greater Bengaluru Area (Hybrid)/ Greater Hyderabad
we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.
Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.
our architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.
. Location: Hyderabad/Bangalore
We are actively seeking Physical Design Engineers based in Hyderabad OR Bangalore
Required competences - Experience
15-25 years’ experience in the semiconductor industry, with min. 5 years in a digital Physical Design technical leadership role
Experience on modern semiconductor process technologies including 28nm, 14/16nm, 7nm
Experienced user of EDA tools for design and verification such as, Cadence Genus and Innovus, LEC, Calibre/PVS DRC/LVS, parasitics extraction, EM and IR drop, ESD, etc.
Expertise in Timing Constraints and Static Timing Analysis (STA)
Experience in CPF/UPF technologies and flows is highly desirable
Exposure to flip-chip package technologies and wire bond package technologies
Experience in hierarchical floor planning and implementation
Experience in release management and tape out procedures
Experience in library setup and flow development with focus on cross project reusability
Experience in DFT methodologies and implementation schemesRequired
Competencies – Skills
Required competences - Skills
Good understanding of RTL to GDS implementation flow (synthesis, P&R, LEC, PV)
Self-motivated, with strong sense of ownership and responsibility. Good communicator and team player
Good scripting capabilities (shell, TCL, Python, make) and good understanding of data management (revision control system)
Responsibility and Authority
Responsibility and Authority
As a Physical Design Engineer, you will work closely with the Architecture, RTL, DFT teams to ensure first-time-right high-volume silicon production
Timing constraints improvement and timing constraints validation, signoff Static Timing Analysis and block-level timing closure
Synthesis, block level floor-planning, power grid design, place & route, clock tree synthesis, electromigration / IR-Drop analysis, power/signal integrity analysis, crosstalk analysis, formal equivalence checking and physical verification (DRC / LVS / Antenna)
Participate in developing improvements to scripts/methodologies/flows
Interact closely with the design team to understand requirements and implement solutions as also helping on providing design views for use with digital PD flows (LIB, LEF, DEF, GDS, SPEF, etc.)
Support IP and chip level integration
Support and interact with customers on requirements and IP delivery
Manage workload and schedule and report to internal management team
Education
Bachelors/Masters of Engineering in Electronics and Electrical Engineering/Computer Science (equivalent or higher)
Contact
Uday
muday_bhaskar@yahoo.com
Mulya Technologies
"Mining the Knowledge Community"
Show more Show less