Senior Principal Physical Design Engineer (Top-Level Floorplanning & STA)

We are looking for a Senior Principal Physical Design Engineer to own the top-level floorplan, global power networks, and timing budgets for our next-generation architecture.


Requirement
Advanced Chip Ownership: Proven track record of owning full-chip top-level integration, floorplanning, and hierarchical design
Dual-Tool Fluency: Expert-level mastery of both Cadence Innovus and Synopsys Fusion Compiler
Sign-off Expertise: Strong background in top-level SDC authoring, timing budgets, and EM/IR sign-off workflows
Ecosystem Management: Exceptional collaboration skills to bridge technical gaps between internal block owners and external ASIC/IP vendors
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