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Senior Principal GPU verification Engineer
Accepting applicationsNXP Semiconductors · Bengaluru, Karnataka, India
Full-Time Mid_senior RTLSystemVerilogUVMVerilogmentor
Estimated market salary
₹37-67 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
15 Jun
Category
Verification
Experience
Mid_senior
Country
India
GPU verification lead
In this role you will be responsible for verifying complex GPU IPs and subsystems, ensuring functional correctness, performance, and first-pass silicon success, collaborating with global design and architecture teams
Key Responsibilities
Develop and execute verification plans for GPU IP blocks (vector graphics, shader cores, memory interfaces and caches)
Build scalable SystemVerilog/UVM-based verification environments with reusable UVM components (agents, monitors, scoreboards)
Develop models for GPU command processing, memory transactions and cache coherency
Lead and mentor junior verification engineers
Own end-to-end IP verification sign-off
Manage regressions and debug failures
Track coverage metrics and verification closure
Required Expertise
Experience: 13+ years
Strong experience in SystemVerilog, UVM, and Verilog
Good understanding of Functional verification methodologies
Assertions (SVA) and coverage
Experience debugging complex RTL and testbench issues
Experience in Formal verification is an added plus
More information about NXP in India...
Show more Show less
In this role you will be responsible for verifying complex GPU IPs and subsystems, ensuring functional correctness, performance, and first-pass silicon success, collaborating with global design and architecture teams
Key Responsibilities
Develop and execute verification plans for GPU IP blocks (vector graphics, shader cores, memory interfaces and caches)
Build scalable SystemVerilog/UVM-based verification environments with reusable UVM components (agents, monitors, scoreboards)
Develop models for GPU command processing, memory transactions and cache coherency
Lead and mentor junior verification engineers
Own end-to-end IP verification sign-off
Manage regressions and debug failures
Track coverage metrics and verification closure
Required Expertise
Experience: 13+ years
Strong experience in SystemVerilog, UVM, and Verilog
Good understanding of Functional verification methodologies
Assertions (SVA) and coverage
Experience debugging complex RTL and testbench issues
Experience in Formal verification is an added plus
More information about NXP in India...
Show more Show less
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