Senior Principal Engineer, Design Verification

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Group Description
Group Description
The Data Center Engineering organization designs, builds, and integrates the processor, coherent cache, interconnect fabric, and the IO-bridge. The team works across Architecture, RTL, Verification, Physical Design disciplines to deliver high-performance, low-power SoCs for use in the cloud / data center and networking equipment including servers, switches, routers, secure gateways, firewall, network monitoring, and smartNICs.

What You Can Expect

• Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers using System Verilog and UVM methodology.
• Analyze designs and architectures to develop test strategies that will ensure functional correctness. 
• Develop verification testplan and write tests using random techniques and coverage analysis, and work with designers to ensure it is complete.
• Debug failures and work with designers to resolve issues.
• Contribute and drive the development and future direction of SoC verification methodologies and environments. 
• Independently proposes and defines new high-level technical work
• Provide leadership for a geographically dispersed team of verification professionals in pre-silicon validation of a highly complex SoC design. 

What We're Looking For

• Bachelor’s degree in Electrical engineering, Electronics, Computer engineering, or related fields with 15+ years of experience.
  Master’s degree and/or PhD in Electrical engineering, Electronics, Computer engineering, or related fields with 10+ years of experience.
• PhD in Electrical engineering, Electronics, Computer engineering, or related fields with 8+ years of experience.
• Strong experience in architecture and implementation of complex/random verification testbench environments using System Verilog/UVM.
• 10+ years of direct hands-on verification experience at block, subsystem and full chip level contexts.
• Technical leadership experience in driving SoC teams with multi domain technical expertise for validating SoCs.
• Strong experience with developing and executing detailed verification test-plans with coverage.
• Extensive experience with scripting languages such as Python or Perl and EDA verification tools, as well as bug tracking and regression mechanisms.
• Expertise in cross functional collaboration for driving outcomes and to participate in problem-solving and quality improvement activities.
• Expertise in guiding and mentoring technical teams for successful execution.
• Ability to generate ideas, take up initiatives and drive the verification productivity gains
• Must have the ability to define problems, issues, and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets.
• Must have the ability to multi-task in a fast-paced environment.

Expected Base Pay Range (USD)

204,900 - 303,250, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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