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Senior Principal Engineer, Analog IC Design

Accepting applications

Marvell · Santa Clara, United States, North America

Full-Time Senior AIAnalogCadenceFinFETMentor
Posted
23h ago
Category
Design
Experience
Senior
Country
United States

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

As a member of Marvell's Central Engineering organization, there is tremendous opportunity to design IP that will be utilized within SoC's across multiple industry segments serviced by Marvell's other business units. These include high speed serial communication cores which support network switching fabric, datacenter, AI/ML sockets, automotive ethernet, electrical to optical transition, IoT, storage and more.

What You Can Expect

Design high speed analog to digital converters. Design the latest high-performance transceivers and other critical analog designs for Marvell's core products. Participate in circuit architecture, circuit implementation, design review, layout, and silicon validation in the following areas: Analog-to-digital converters (ADC), Digital-to-analog converters (DAC), Phase-Locked Loop (PLL), filter, adaptive equalizers, finite-impulse response (FIR) filter, and decision-feedback equalizer (DFE), serializer-deserializer (Serdes), clock and data recovery (CDR) circuits, and phase-locked loop (PLL) or other timing circuits. Create analog circuit solutions to address performance challenges achieving the lowest possible power and area footprint. Provide technical leadership to a team of IC designers to enable successful on-time releases. Understand how the current work items fit into the larger design cycle and recognize and resolve obstacles before they impact release schedules. Manage multiple assignments with overlapping program timeframes. Provide mentorship and supervision to junior analog design engineers and mask designers to ensure best design practices are adopted while delivering industry leading competitive IP solutions. $275,000.00 - $305,000.00 per year.

What We're Looking For

Master’s or foreign equivalent degree in Electrical/Electronic Engineering, Computer Science/Engineering, or a related field and five (5) years of experience in the job offered or related occupation.

Experience must include five (5) years with each of the following:

•    Cadence Design System (schematic composer, layout virtuoso, EXL, spectre, Pnoise).
•    Post extraction netlist simulations and use of scripts to post process and debug.
•    TSMC FinFET technology device rules, reliability.
•    Status reporting to management.
•    Architecture and circuit design of industry competitive data converters and other analog circuits.
•    Driving silicon debug and validation activities for analog Ips.
•    Mentoring and supervising analog design engineers.
•    Project planning and design cycle management (concept architecture to silicon).
•    Supervising complex FinFET layout development ensuring quality and performance metrics are met.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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