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Senior Principal Digital Design Engineer
Accepting applicationsNXP Semiconductors · Bengaluru, Karnataka, India
Full-Time Mid_senior ARMDFTRTLSoCmentor
Estimated market salary
₹18-33 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
15 Jun
Category
Design
Experience
Mid_senior
Country
India
NXP Semiconductors enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better and safer. As the world leader in secure connectivity solutions for embedded applications, we are driving innovation in the secure connected vehicle, end-to-end security & privacy and smart connected solutions markets. To further strengthen our team in Bangalore we have the following position vacant: Digital Design Lead
Responsibilities
Ownership of a sub system
Digital circuit design and optimization (power, timing, area) including reusability
IP evaluation and selection
RTL coding
Support functional simulations, give inputs for functional coverage
SoC clock architecture
Coverage analysis, lint and CDC analysis
Support for backend in timing closure, develop timing constraints
Support design for testability
Support for power analysis
Guide and mentor team members
Review outputs from the design team
HW-SW co-design and alignment with SW engineers
Debug issues in netlist verification (0 delay, SDF simulations)
Support for evaluation and verification of silicon
Documentation (Datasheet, design reports)
Support analysis of field problems
Effort estimation and inputs for planning.
Profile
12+ years of experience in digital design, SoC integration.
Expert in AMBA protocols
Knowledge of ARM based SoC architecture
Familiar with CPF/UPF formats
Good knowledge of digital timing concepts, DFT concepts
Experience in using functional simulation tools, synthesis tools, Spyglass
Good communication skills in English
Good team player eager to develop best in class products
More information about NXP in India...
Show more Show less
Responsibilities
Ownership of a sub system
Digital circuit design and optimization (power, timing, area) including reusability
IP evaluation and selection
RTL coding
Support functional simulations, give inputs for functional coverage
SoC clock architecture
Coverage analysis, lint and CDC analysis
Support for backend in timing closure, develop timing constraints
Support design for testability
Support for power analysis
Guide and mentor team members
Review outputs from the design team
HW-SW co-design and alignment with SW engineers
Debug issues in netlist verification (0 delay, SDF simulations)
Support for evaluation and verification of silicon
Documentation (Datasheet, design reports)
Support analysis of field problems
Effort estimation and inputs for planning.
Profile
12+ years of experience in digital design, SoC integration.
Expert in AMBA protocols
Knowledge of ARM based SoC architecture
Familiar with CPF/UPF formats
Good knowledge of digital timing concepts, DFT concepts
Experience in using functional simulation tools, synthesis tools, Spyglass
Good communication skills in English
Good team player eager to develop best in class products
More information about NXP in India...
Show more Show less
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