Senior Principal Design Engineer

The Candidate Shall Be Responsible For

SoC u-Architecture for Clocking, Reset, Core & Interconnects, Power Management, Debug & Trace, Functional Safety, Security, IP/Subsystems integration etc.
SoC RTL Integration using state-of-the-art tools, flows & methodologies
LINT/CDC/RDC signoffs for the highest design quality
Handoff checks including Verification smokesuite and express Synthesis
Continuous learning using 3X5 Why based Root cause analysis, DFMEA, Lessons Learned for the product family
Requirements management and traceability including IS026262 / CMMi and other compliance requirements, working closely with System Architects, Applications, Design & Verification teams, Product & Test engineering, PMO and support functions
Overseeing technical documentation in close collaboration with information development team
Conducting IP Integration reviews, BE reports reviews for concurrent engineering
Driving key SoC design methodologies in close collaboration with global cross functional functional teams, Design Enablement etc.
Mentoring other engineers based on deep core competence and expertise

Soft Skills Expected

Excellent collaboration skills and team work
Excellent verbal & written communication skills
Excellent presentation skills
Passion and can-do attitude

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