LT
Senior Pixel Design Engineer (CIS)
Accepting applicationsLedgent Technology · Irvine, CA
Full-Time Mid_senior AnalogCMOSCadenceSynopsysai
Posted
1d ago
Category
Test
Experience
Mid_senior
Country
United States
Full-Time | Open to Consulting (Part-Time ~20 hrs/week)
Salary: $140K+ (DOE; higher for Senior/Manager-level candidates)
Open to provide Visa sponsorship or Visa Tranfer for the right candidate
Role Overview
We are seeking an experienced Pixel Design Engineer with direct experience in CMOS Image Sensor (CIS) pixel layout. This is a critical, high-impact role supporting ongoing projects and next-generation pixel development.
This is not a general analog or mixed-signal role-hands-on pixel design experience is required.
You will work closely with a small, highly skilled team to design, optimize, and implement pixel layouts, contributing immediately to active programs.
Key Responsibilities
Design and optimize CIS pixel layouts (front-end, back-end, and optical structures)
Perform pixel-level layout optimization considering:
Process flow and design rules
Timing constraints and noise performance
Signal interference via capacitance extraction
Develop and implement pixel array floorplans
Execute DRC, LVS validation across pixel arrays
Design special pixels (e.g., dark reference pixels)
Collaborate across teams on pixel-to-readout interfaces
Contribute to optical structure design and layout alignment
Required Qualifications (Must-Have)
BS + 5 years OR MS + 3+ years of hands-on CIS pixel layout experience
Proven expertise with IC layout and parasitic capacitance extraction
Strong understanding of:
CIS pixel physics
Timing and operational principles
Proficiency with EDA tools:
Cadence Virtuoso (layout)
Synopsys Sentaurus TCAD (Sprocess, Sdevice, SDE, Raphael)
Programming skills (moderate level)
Degree in Electrical Engineering, Physics, or Photonics
Important: Analog or mixed-signal-only backgrounds without pixel experience will not be considered.
Preferred Qualifications
Experience with CMOS image sensor process integration
Knowledge of device physics and optics
Prior work on advanced pixel technologies or imaging chips
Work Setup & Flexibility
Preferred: Onsite in Irvine, CA
Open to remote candidates (must be able to travel to Irvine ~1 week/month)
Initial onboarding will require onsite presence
Travel expenses covered
Relocation assistance available ($10K-$20K range for strong candidates)
Additional Details
Reports to: Senior Director of Pixel Design
Team: Small, collaborative R&D group (currently rebuilding pixel team)
Work Hours: ~9:30/10 AM - 6/7 PM PST (includes collaboration with Asian team)
Visa Sponsorship: Available
Why Join Us
Work on cutting-edge camera sensor technology
High-impact role with immediate contribution expectations
Small team with strong ownership and innovation culture
Flexible hiring approach (full-time or consulting options available)
All qualified applicants will receive consideration for employment without regard to race, color, national origin, age, ancestry, religion, sex, sexual orientation, gender identity, gender expression, marital status, disability, medical condition, genetic information, pregnancy, or military or veteran status. We consider all qualified applicants, including those with criminal histories, in a manner consistent with state and local laws, including the California Fair Chance Act, City of Los Angeles' Fair Chance Initiative for Hiring Ordinance, and Los Angeles County Fair Chance Ordinance.
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Salary: $140K+ (DOE; higher for Senior/Manager-level candidates)
Open to provide Visa sponsorship or Visa Tranfer for the right candidate
Role Overview
We are seeking an experienced Pixel Design Engineer with direct experience in CMOS Image Sensor (CIS) pixel layout. This is a critical, high-impact role supporting ongoing projects and next-generation pixel development.
This is not a general analog or mixed-signal role-hands-on pixel design experience is required.
You will work closely with a small, highly skilled team to design, optimize, and implement pixel layouts, contributing immediately to active programs.
Key Responsibilities
Design and optimize CIS pixel layouts (front-end, back-end, and optical structures)
Perform pixel-level layout optimization considering:
Process flow and design rules
Timing constraints and noise performance
Signal interference via capacitance extraction
Develop and implement pixel array floorplans
Execute DRC, LVS validation across pixel arrays
Design special pixels (e.g., dark reference pixels)
Collaborate across teams on pixel-to-readout interfaces
Contribute to optical structure design and layout alignment
Required Qualifications (Must-Have)
BS + 5 years OR MS + 3+ years of hands-on CIS pixel layout experience
Proven expertise with IC layout and parasitic capacitance extraction
Strong understanding of:
CIS pixel physics
Timing and operational principles
Proficiency with EDA tools:
Cadence Virtuoso (layout)
Synopsys Sentaurus TCAD (Sprocess, Sdevice, SDE, Raphael)
Programming skills (moderate level)
Degree in Electrical Engineering, Physics, or Photonics
Important: Analog or mixed-signal-only backgrounds without pixel experience will not be considered.
Preferred Qualifications
Experience with CMOS image sensor process integration
Knowledge of device physics and optics
Prior work on advanced pixel technologies or imaging chips
Work Setup & Flexibility
Preferred: Onsite in Irvine, CA
Open to remote candidates (must be able to travel to Irvine ~1 week/month)
Initial onboarding will require onsite presence
Travel expenses covered
Relocation assistance available ($10K-$20K range for strong candidates)
Additional Details
Reports to: Senior Director of Pixel Design
Team: Small, collaborative R&D group (currently rebuilding pixel team)
Work Hours: ~9:30/10 AM - 6/7 PM PST (includes collaboration with Asian team)
Visa Sponsorship: Available
Why Join Us
Work on cutting-edge camera sensor technology
High-impact role with immediate contribution expectations
Small team with strong ownership and innovation culture
Flexible hiring approach (full-time or consulting options available)
All qualified applicants will receive consideration for employment without regard to race, color, national origin, age, ancestry, religion, sex, sexual orientation, gender identity, gender expression, marital status, disability, medical condition, genetic information, pregnancy, or military or veteran status. We consider all qualified applicants, including those with criminal histories, in a manner consistent with state and local laws, including the California Fair Chance Act, City of Los Angeles' Fair Chance Initiative for Hiring Ordinance, and Los Angeles County Fair Chance Ordinance.
Show more Show less