ED
Senior Physical Design (PNR) Engineer
Accepting applicationsEximietas Design · San Francisco Bay Area
Full-Time Mid_senior CadenceInnovusPythonRTLSoC
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
United States
Senior Physical Design (PNR) Engineer – Multiple Roles
Company: Eximietas Design
Locations: San Jose or San Diego preferred (other locations can be discussed)
Experience: 10+ years
Type: Full-Time
Eximietas Design is expanding its Physical Design team and hiring Senior PNR Engineers to support advanced-node (5nm/3nm) semiconductor programs. We are looking for engineers who bring strong technical ownership in Floorplanning, Top-Level Integration, or Block-Level PNR Implementation.
If you thrive on solving complex physical design challenges and want to help drive next-generation SoC designs, we want to talk to you.
Open Positions
We are hiring across three specialisation areas within Physical Design:
Senior PD Engineer – Floorplanning
Senior PD Engineer – Top-Level PNR / Routing
Senior PD Engineer – Block-Level PNR
What You Will Do
Floorplanning
Develop efficient, congestion-aware floorplans for blocks and top-level SoCs
Own macro placement, pin assignment, and power grid planning
Drive early feasibility for timing, IR, density, and overall PPA targets
Top-Level PNR / Integration
Lead top-level routing and physical integration across hierarchical designs
Identify and resolve congestion, routing issues, and signoff-driven ECOs
Ensure alignment and consistency across block owners and timing/signoff teams
Block-Level PNR (Standard Cell Implementation)
Execute complete block implementation: placement → CTS → routing → timing closure
Achieve clean timing, DRC, and power results across MCMM scenarios
Implement ECOs to optimise PPA and accelerate convergence at advanced nodes
What You Bring
10+ years of hands-on Physical Design / PNR experience
Strong proficiency with Cadence Innovus (required); exposure to Tempus/Voltus is a plus
Familiarity with Synopsys ICC2 or Fusion Compiler (preferred but not mandatory)
Deep understanding of advanced-node challenges (MCMM, OCV, SI, IR, EM, density)
Strong scripting skills (Tcl, Python, Shell) for flow automation and debugging
Ability to collaborate effectively across RTL, Architecture, Verification, and Signoff teams
Experience working on 7nm / 5nm / 3nm nodes is a strong advantage
Why Join Eximietas Design
Work on cutting-edge advanced-node semiconductor programs
High-impact roles with strong technical ownership
A collaborative, engineering-centric culture
Competitive compensation and growth opportunities
How to Apply
Apply with your resume and specify the area you are most experienced in:
Floorplanning
Top-Level PNR
Block-Level PNR
We look forward to meeting top Physical Design talent ready to shape next-generation silicon.
Apply/refer/Discuss email mohini.tyagi@eximietas.design
Show more Show less
Company: Eximietas Design
Locations: San Jose or San Diego preferred (other locations can be discussed)
Experience: 10+ years
Type: Full-Time
Eximietas Design is expanding its Physical Design team and hiring Senior PNR Engineers to support advanced-node (5nm/3nm) semiconductor programs. We are looking for engineers who bring strong technical ownership in Floorplanning, Top-Level Integration, or Block-Level PNR Implementation.
If you thrive on solving complex physical design challenges and want to help drive next-generation SoC designs, we want to talk to you.
Open Positions
We are hiring across three specialisation areas within Physical Design:
Senior PD Engineer – Floorplanning
Senior PD Engineer – Top-Level PNR / Routing
Senior PD Engineer – Block-Level PNR
What You Will Do
Floorplanning
Develop efficient, congestion-aware floorplans for blocks and top-level SoCs
Own macro placement, pin assignment, and power grid planning
Drive early feasibility for timing, IR, density, and overall PPA targets
Top-Level PNR / Integration
Lead top-level routing and physical integration across hierarchical designs
Identify and resolve congestion, routing issues, and signoff-driven ECOs
Ensure alignment and consistency across block owners and timing/signoff teams
Block-Level PNR (Standard Cell Implementation)
Execute complete block implementation: placement → CTS → routing → timing closure
Achieve clean timing, DRC, and power results across MCMM scenarios
Implement ECOs to optimise PPA and accelerate convergence at advanced nodes
What You Bring
10+ years of hands-on Physical Design / PNR experience
Strong proficiency with Cadence Innovus (required); exposure to Tempus/Voltus is a plus
Familiarity with Synopsys ICC2 or Fusion Compiler (preferred but not mandatory)
Deep understanding of advanced-node challenges (MCMM, OCV, SI, IR, EM, density)
Strong scripting skills (Tcl, Python, Shell) for flow automation and debugging
Ability to collaborate effectively across RTL, Architecture, Verification, and Signoff teams
Experience working on 7nm / 5nm / 3nm nodes is a strong advantage
Why Join Eximietas Design
Work on cutting-edge advanced-node semiconductor programs
High-impact roles with strong technical ownership
A collaborative, engineering-centric culture
Competitive compensation and growth opportunities
How to Apply
Apply with your resume and specify the area you are most experienced in:
Floorplanning
Top-Level PNR
Block-Level PNR
We look forward to meeting top Physical Design talent ready to shape next-generation silicon.
Apply/refer/Discuss email mohini.tyagi@eximietas.design
Show more Show less