Senior Physical Design Engineer

Physical Design and STA Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years chasing nanoseconds that matter, closing timing on designs where a single path violation can sink a tapeout and where "close enough" does not exist. High performance memory interfaces like DDR, LPDDR, and HBM are your territory. You know what it takes to get a chip across the finish line when you are juggling multiple corners, asynchronous crossings, and a design that refuses to converge at 3am two weeks before signoff.

You do not just run PrimeTime and hope for the best. You understand the constraints, you know when they are wrong, and you are not afraid to push back when an RTL change or a floorplan decision is making your job harder than it needs to be. Scripting is second nature to you. Whether it is Tcl, Python, or Perl, you automate the repetitive stuff so you can focus on the hard problems that actually require a human brain.

Working across global teams does not faze you. You can explain a timing arc to an engineer in a different timezone, present a closure strategy to a lead, and still find time to implement the ECO that fixes the bug no one else caught. At Synopsys, you will work on IP that powers the most advanced chips in the world, and the timing you close will ship in products that millions of people use every day.

What You'll Be Doing

Close timing on high performance memory IP designs including DDR, LPDDR, HBM, and SoC blocks, driving convergence across multiple process corners and operating modes
Perform static timing analysis at the chip level using PrimeTime, identifying critical paths, analyzing timing violations, and implementing fixes that actually stick
Implement engineering change orders to resolve functional bugs and timing issues without breaking what already works
Write and maintain automation scripts in Python, Perl, Tcl, and shell to streamline STA flows, constraint generation, reporting, and ECO implementation
Work with cross-functional teams including RTL designers, physical design engineers, and verification teams to ensure timing, power, and area requirements are met from floorplan through tapeout
Handle asynchronous timing closure, clock domain crossings, and multi-mode multi-corner analysis on designs where margins are tight and stakes are high
Use PrimeTime ECO and DMSA to optimize timing paths and drive signoff quality across complex IP blocks

The Impact You Will Have

Your timing closure work will directly enable successful tapeouts of high performance memory IP used in cutting-edge AI, mobile, and data center applications
The automation frameworks you build will accelerate STA turnaround time and improve efficiency across the entire physical design flow
Your ability to catch and fix timing issues early will prevent costly respins and keep product schedules on track
The quality of your analysis and constraint development will raise the bar for timing signoff across Synopsys IP portfolios
Your collaboration with global teams will ensure that timing considerations are integrated into design decisions from the start, not discovered at the end
The ECOs you implement will resolve critical bugs and timing violations without introducing new risk or delay
Your contributions will help Synopsys deliver IP that meets the performance and power targets our customers depend on to compete in the semiconductor market

What You'll Need

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or a related field
5+ years of hands-on experience in static timing analysis, with a strong focus on chip-level timing closure
Deep expertise in PrimeTime, including PrimeTime ECO and DMSA, for timing analysis and optimization
Proven experience closing timing on high performance designs such as DDR, LPDDR, HBM, or similar memory interfaces
Strong scripting skills in Tcl and Python, with working knowledge of Perl and shell scripting for automation
Solid understanding of timing constraints, asynchronous timing analysis, and multi-corner multi-mode closure techniques
Experience working in an RTL to GDS implementation flow is a strong plus, particularly if you have touched physical design or floorplanning

Who You Are

You can look at a timing report with 500 violations and immediately know which three paths are the ones that actually matter and need to be fixed first
You write scripts that other engineers can actually read and use, not just throwaway code that works once and breaks the next day
When a design is not converging, you do not just try random fixes. You dig into the data, understand the root cause, and propose a solution that makes sense
You communicate clearly with engineers across disciplines and timezones, whether you are explaining a constraint issue to an RTL designer or presenting a closure plan to a project lead
You stay calm under pressure. Tapeout schedules slip, requirements change, and bugs appear late, and you know how to prioritize and keep moving without losing quality
You are comfortable challenging assumptions. If a constraint looks wrong or a timing goal seems unrealistic, you say so and back it up with data

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process
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