Senior Physical Design Engineer

ASIC Physical Design Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the physical design trenches, taking designs from RTL to GDS and learning that the difference between a chip that tapes out and one that stalls at signoff is usually a decision you made during floorplanning. You know that timing closure is not a single event, it is a continuous negotiation between what the RTL wants and what the silicon will tolerate. You have debugged enough EM violations at 2 a.m. to know that power planning is not optional, and you have fixed enough DRC issues to recognize when a problem is yours versus when it is time to loop in the foundry.

You think in flows, not just tools. When you see a repetitive task, you script it. When a signoff check fails, you do not just fix the symptom, you understand the root cause and update the methodology so it does not happen again. You are comfortable sitting with front-end teams to push back on unrealistic timing budgets and equally comfortable diving into RedHawk reports to isolate an IR drop issue that is killing your margin.

At Synopsys, you will work on high-performance interface IPs and subsystems that ship in real products. The technology nodes are advanced, the problems are hard, and the team expects you to own your blocks from synthesis to signoff.

What You'll Be Doing

Own end-to-end physical implementation of high-performance interface IPs, subsystems, and test chips from RTL through synthesis, floorplanning, placement, CTS, routing, and final GDS delivery
Develop timing constraints, perform static timing analysis using PrimeTime, and drive timing closure across multiple corners and modes at advanced process nodes (7nm and below)
Execute power planning strategies, run EM/IR analysis using RedHawk, and resolve power integrity issues to meet signoff requirements
Perform physical verification using IC Validator (ICV), debug and resolve DRC/LVS violations, and coordinate with foundry teams on design rule interpretation and manufacturability
Build and enhance physical design flows using Tcl, Perl, and Python to automate repetitive tasks, improve runtime, and increase design productivity
Collaborate with front-end design, DFT, and verification teams to resolve design issues, optimize PPA (power, performance, area), and ensure clean handoffs between stages
Contribute to subsystem-level integration, managing hierarchical implementation across multiple IP blocks and ensuring robust signoff at the top level

The Impact You Will Have

Enable successful tape-outs of cutting-edge interface IPs and subsystems that power next-generation semiconductor products across multiple industries
Reduce design cycle time by building reusable, automated flows that eliminate manual bottlenecks and improve team efficiency
Ensure power integrity and reliability at advanced nodes, directly impacting product performance and yield in high-volume manufacturing
Catch and resolve physical design issues early in the flow, preventing costly respins and schedule slips downstream
Strengthen the bridge between front-end design intent and back-end physical reality, improving overall design quality and reducing iteration loops
Contribute to Synopsys IP portfolio quality and competitiveness by delivering designs that meet aggressive PPA targets and foundry requirements
Mentor and elevate the physical design practice within the Noida team through methodology improvements and knowledge sharing

What You'll Need

B.Tech or M.Tech in Electrical Engineering, Electronics Engineering, or closely related field
3+ years of hands-on experience in ASIC physical implementation, including synthesis, place and route, and signoff
Proven track record with at least one recent project tape-out where you owned physical design responsibilities through GDS delivery
Strong working knowledge of industry-standard tools including PrimeTime for STA, RedHawk for EM/IR analysis, and IC Validator (ICV) for physical verification
Solid understanding of advanced-node physical design challenges (7nm, 5nm, or below) including multi-patterning, complex design rules, and signoff closure strategies
Scripting proficiency in Tcl, Perl, or Python for flow automation and CAD methodology development
Experience with high-performance or high-speed interface IP design (SerDes, DDR, PCIe, or similar) is a strong plus

Who You Are

You can look at a floorplan and immediately spot the congestion hotspot or the clock domain that is going to cause problems three weeks from now
You do not wait for perfect constraints from the front-end team, you work with what you have, flag what is missing, and build margin where you need it
You know when to escalate a foundry DRC issue and when to just rework the layout, and you can explain the tradeoff to your manager in two sentences
You treat your scripts and flows like production code, commented, version-controlled, and built to be reused by someone else six months later
You are comfortable presenting timing closure status in a design review, defending your approach, and adjusting based on feedback from architects or leads
You stay current on new tool features and methodology shifts because you know that what worked at 28nm does not always scale to 5nm

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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