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Senior Physical Design Engineer
Accepting applicationsOho Group · San Francisco Bay Area
Full-Time Mid_senior AIASICCadenceCalibreDDR
Posted
2d ago
Category
Design
Experience
Mid_senior
Country
United States
Principal/Senior Physical Design Engineer - Up to $300k + Equity | San Jose
I’m working with one of the most ambitious and exceptionally well-capitalised semiconductor startups in the US, developing a new class of high-bandwidth memory technology intended to address one of the fundamental bottlenecks in AI computing.
The company has assembled a genuinely world-class leadership team spanning advanced process technology, memory, 3D integration, SerDes and AI architecture. With major strategic backing and a clear path towards commercial silicon, it has the potential to become one of the most important semiconductor companies of its generation.
They are now expanding their Physical Design team and hiring at both Senior and Lead/Principal level.
Responsibilities
Own advanced-node physical implementation from floorplanning through signoff
Drive placement, CTS, routing, timing closure and post-route ECOs
Integrate complex hard macros, PHYs and mixed-signal IP
Resolve congestion, signal-integrity and power-integrity challenges
Perform IR-drop and electromigration analysis
Work closely with RTL, STA, circuit-design and architecture teams
Deliver production-quality silicon through physical verification and tapeout
At Lead/Principal level, define full-chip methodology, guide hierarchical implementation and mentor other engineers
Ideal experience
Deep, recent experience with Cadence Innovus
Advanced-node ASIC/SoC implementation at 7nm, 5nm or below
Complete netlist-to-GDSII ownership
Strong floorplanning, placement, CCOPT/CTS, routing and timing-closure expertise
Experience with Voltus or RedHawk and Calibre DRC/LVS
Multiple successful silicon tapeouts
Strong Tcl scripting and flow-automation capability
Experience with DDR, LPDDR, HBM, SerDes or other high-speed PHYs is particularly valuable
Hard-macro integration, mixed-signal floorplanning or 3D-IC experience would be highly desirable
Show more Show less
I’m working with one of the most ambitious and exceptionally well-capitalised semiconductor startups in the US, developing a new class of high-bandwidth memory technology intended to address one of the fundamental bottlenecks in AI computing.
The company has assembled a genuinely world-class leadership team spanning advanced process technology, memory, 3D integration, SerDes and AI architecture. With major strategic backing and a clear path towards commercial silicon, it has the potential to become one of the most important semiconductor companies of its generation.
They are now expanding their Physical Design team and hiring at both Senior and Lead/Principal level.
Responsibilities
Own advanced-node physical implementation from floorplanning through signoff
Drive placement, CTS, routing, timing closure and post-route ECOs
Integrate complex hard macros, PHYs and mixed-signal IP
Resolve congestion, signal-integrity and power-integrity challenges
Perform IR-drop and electromigration analysis
Work closely with RTL, STA, circuit-design and architecture teams
Deliver production-quality silicon through physical verification and tapeout
At Lead/Principal level, define full-chip methodology, guide hierarchical implementation and mentor other engineers
Ideal experience
Deep, recent experience with Cadence Innovus
Advanced-node ASIC/SoC implementation at 7nm, 5nm or below
Complete netlist-to-GDSII ownership
Strong floorplanning, placement, CCOPT/CTS, routing and timing-closure expertise
Experience with Voltus or RedHawk and Calibre DRC/LVS
Multiple successful silicon tapeouts
Strong Tcl scripting and flow-automation capability
Experience with DDR, LPDDR, HBM, SerDes or other high-speed PHYs is particularly valuable
Hard-macro integration, mixed-signal floorplanning or 3D-IC experience would be highly desirable
Show more Show less