Senior Physical Design Engineer

Job Summary
We are seeking a highly skilled Physical Design Engineer with strong expertise in full-chip and block-level physical implementation. The ideal candidate will have hands-on experience in floorplanning, placement, CTS, routing, timing closure, and physical verification for advanced technology nodes.
Key Responsibilities
Perform RTL-to-GDSII implementation for complex SoCs/IPs.
Develop and execute floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure.
Analyze and fix setup/hold timing violations.
Perform physical verification including DRC, LVS, and ERC checks.
Work closely with RTL, DFT, STA, and Design teams to achieve design closure.
Optimize power, performance, and area (PPA).
Support chip integration and tape-out activities.
Required Skills
Strong experience in Physical Design flow from Netlist to GDSII.
Expertise in:
Floorplanning
Placement & Optimization
Clock Tree Synthesis (CTS)
Routing
Timing Closure
Physical Verification
Hands-on experience with:
Cadence Innovus
Synopsys ICC2
PrimeTime
Tempus
Strong understanding of:
STA
IR Drop Analysis
Signal Integrity (SI)
Power Analysis
Experience with advanced technology nodes (16nm/7nm/5nm/3nm preferred).
Good scripting skills in Tcl, Perl, or Python.
Preferred Qualifications
Experience in CPU, GPU, AI/ML, Networking, or High-Speed SoC designs.
Strong debugging and problem-solving skills.
Excellent communication and teamwork abilities

Show more Show less