MT
Senior Physical Design Engineer
Accepting applicationsMirafra Technologies · San Francisco Bay Area
Full-Time Mid_senior CadenceCalibreInnovusPythonRTL
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
United States
Job Title: Physical Design Engineer
Job Summary:
We are seeking an experienced Physical Design Engineer to lead and implement physical
design across a range of high-volume consumer devices and satellite-related projects. This role
involves end-to-end physical implementation, collaboration with cross-functional teams, and
ownership of physical design methodologies and timing closure.
Key Responsibilities:
• Lead and implement physical design for chips across process nodes ranging from 40nm
to 7nm
• Perform block-level and top-level physical implementation
• Drive floorplanning activities including multi-power domain design, power grid (PG)
planning, block shaping, and clock tree implementation
• Interface with internal and external stakeholders, including Design, IP, and Library teams
• Conduct physical verification at block and chip level
• Perform static and dynamic IR drop analysis, as well as signal and power
electromigration (EM) checks
• Develop methodologies and flows for physical design and timing closure
• Collaborate with Synthesis, STA, and RTL design teams to meet physical
implementation and power intent requirements
• Support ESD, IO padring, and analog integration; experience with packaging types such
as flip-chip and WLCSP is preferred
Required Qualifications:
• Bachelor’s degree in Electrical Engineering with 8+ years of experience, OR Master’s
degree in Electrical Engineering with 10+ years of experience
• Multiple tapeout experience
• Extensive hands-on experience with tools such as Innovus, VCLP, Formality, LEC,
Calibre, and timing closure tools
• Strong expertise with Cadence Innovus (required)
• TCL scripting experience (required); Python is a plus
• Knowledge of physical design flows and methodologies
Show more Show less
Job Summary:
We are seeking an experienced Physical Design Engineer to lead and implement physical
design across a range of high-volume consumer devices and satellite-related projects. This role
involves end-to-end physical implementation, collaboration with cross-functional teams, and
ownership of physical design methodologies and timing closure.
Key Responsibilities:
• Lead and implement physical design for chips across process nodes ranging from 40nm
to 7nm
• Perform block-level and top-level physical implementation
• Drive floorplanning activities including multi-power domain design, power grid (PG)
planning, block shaping, and clock tree implementation
• Interface with internal and external stakeholders, including Design, IP, and Library teams
• Conduct physical verification at block and chip level
• Perform static and dynamic IR drop analysis, as well as signal and power
electromigration (EM) checks
• Develop methodologies and flows for physical design and timing closure
• Collaborate with Synthesis, STA, and RTL design teams to meet physical
implementation and power intent requirements
• Support ESD, IO padring, and analog integration; experience with packaging types such
as flip-chip and WLCSP is preferred
Required Qualifications:
• Bachelor’s degree in Electrical Engineering with 8+ years of experience, OR Master’s
degree in Electrical Engineering with 10+ years of experience
• Multiple tapeout experience
• Extensive hands-on experience with tools such as Innovus, VCLP, Formality, LEC,
Calibre, and timing closure tools
• Strong expertise with Cadence Innovus (required)
• TCL scripting experience (required); Python is a plus
• Knowledge of physical design flows and methodologies
Show more Show less