Senior Physical Design Engineer

Key Responsibilities:
Perform RTL-to-GDSII implementation (Floorplanning, Placement, CTS, Routing)
Handle timing closure, congestion, and power optimization
Work on STA (Static Timing Analysis) and fix timing violations
Perform physical verification (DRC, LVS, ERC)
Collaborate with RTL, DFT, and STA teams
Work on ECO implementation and signoff flows
Ensure design meets PPA (Power, Performance, Area) targets
Required Skills:
Strong experience in Physical Design flow
Hands-on with tools like:
Synopsys ICC2 / Fusion Compiler
Cadence Innovus
PrimeTime (STA)
Good understanding of:
Timing constraints, clock tree synthesis
Signal integrity, IR drop, EM
Experience in advanced nodes (7nm/5nm/3nm is a plus)
Scripting knowledge: TCL / Python / Perl
Preferred Qualifications:
Experience with low power design (UPF/CPF)
Knowledge of DFT and scan integration
Exposure to high-speed or networking SoCs
Good debugging and problem-solving skills
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