LD
Senior Physical Design Engineer
Accepting applicationsleadIC Design Pvt Ltd · Bengaluru, Karnataka, India
Full-Time Mid_senior Physical DesignSynthesisSTA
Estimated market salary
₹20-36 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
20h ago
Category
Design
Experience
Mid_senior
Country
India
Company Description
LeadIC Design Pvt Ltd accelerates semiconductor innovation through full-stack VLSI engineering expertise, supporting the complete chip development lifecycle for global semiconductor companies. Founded in 2018, the company has grown into a trusted partner with engineering teams across India and Canada, delivering high-quality design services tailored to product-focused teams. LeadIC’s capabilities span custom, memory, and analog layout, analog/mixed-signal circuit design, digital design and RTL development, design verification, physical design, STA, DFT, physical verification, IP characterization, and FPGA-based prototyping. The organization emphasizes an engineering culture built on ownership, quality-driven execution, and flexible partnership models that adapt to diverse technical and business needs. Long-term global client relationships reflect LeadIC’s reliability and commitment to enabling successful silicon products.
Role Description
The Senior Physical Design Engineer will lead and execute end-to-end physical design flows, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, optimization, and timing closure for complex SoCs. The role involves collaborating closely with logic design, RTL, verification, and circuit design teams to ensure robust implementation and sign-off across timing, power, and signal integrity. The engineer will drive physical verification activities, support DFT and integration requirements, and contribute to methodology improvements and tool flow optimization. Responsibilities also include mentoring junior engineers, reviewing design work, and maintaining best practices for scalability and quality.
This is a full-time, on-site role based in Hyderabad.
Qualifications
Candidates must have 5+ years of relevant hands-on experience in Physical Design.
Hands-on experience working with TSMC advanced technology nodes below 12nm is mandatory.
Strong hands-on experience with Cadence Innovus is mandatory.
Candidates should possess strong skills in end-to-end Physical Design, including synthesis, floorplanning, placement, CTS, routing, optimization, and timing closure.
Candidates should possess skills in Physical Verification, covering DRC, LVS, ERC, and sign-off checks for advanced technology nodes.
Candidates should have a strong understanding of STA, power analysis, signal integrity, and physical design sign-off methodologies.
Proficiency with industry-standard EDA tools, particularly Cadence Innovus, along with familiarity with Synopsys and Siemens EDA tools, is preferred.
Strong problem-solving abilities, attention to detail, and the capability to work effectively in cross-functional engineering teams are required.
Prior experience in leading physical design activities for multi-million gate designs or complex SoCs is highly beneficial.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related discipline, or equivalent practical experience.
Mandatory Requirements
5+ years of relevant Physical Design experience.
Hands-on experience with TSMC technology nodes below 12nm.
Strong hands-on expertise with Cadence Innovus.
Interested candidates can DM me directly on LinkedIn or share their updated resume at nagu.ms@leadicdesign.com.
Show more Show less
LeadIC Design Pvt Ltd accelerates semiconductor innovation through full-stack VLSI engineering expertise, supporting the complete chip development lifecycle for global semiconductor companies. Founded in 2018, the company has grown into a trusted partner with engineering teams across India and Canada, delivering high-quality design services tailored to product-focused teams. LeadIC’s capabilities span custom, memory, and analog layout, analog/mixed-signal circuit design, digital design and RTL development, design verification, physical design, STA, DFT, physical verification, IP characterization, and FPGA-based prototyping. The organization emphasizes an engineering culture built on ownership, quality-driven execution, and flexible partnership models that adapt to diverse technical and business needs. Long-term global client relationships reflect LeadIC’s reliability and commitment to enabling successful silicon products.
Role Description
The Senior Physical Design Engineer will lead and execute end-to-end physical design flows, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, optimization, and timing closure for complex SoCs. The role involves collaborating closely with logic design, RTL, verification, and circuit design teams to ensure robust implementation and sign-off across timing, power, and signal integrity. The engineer will drive physical verification activities, support DFT and integration requirements, and contribute to methodology improvements and tool flow optimization. Responsibilities also include mentoring junior engineers, reviewing design work, and maintaining best practices for scalability and quality.
This is a full-time, on-site role based in Hyderabad.
Qualifications
Candidates must have 5+ years of relevant hands-on experience in Physical Design.
Hands-on experience working with TSMC advanced technology nodes below 12nm is mandatory.
Strong hands-on experience with Cadence Innovus is mandatory.
Candidates should possess strong skills in end-to-end Physical Design, including synthesis, floorplanning, placement, CTS, routing, optimization, and timing closure.
Candidates should possess skills in Physical Verification, covering DRC, LVS, ERC, and sign-off checks for advanced technology nodes.
Candidates should have a strong understanding of STA, power analysis, signal integrity, and physical design sign-off methodologies.
Proficiency with industry-standard EDA tools, particularly Cadence Innovus, along with familiarity with Synopsys and Siemens EDA tools, is preferred.
Strong problem-solving abilities, attention to detail, and the capability to work effectively in cross-functional engineering teams are required.
Prior experience in leading physical design activities for multi-million gate designs or complex SoCs is highly beneficial.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related discipline, or equivalent practical experience.
Mandatory Requirements
5+ years of relevant Physical Design experience.
Hands-on experience with TSMC technology nodes below 12nm.
Strong hands-on expertise with Cadence Innovus.
Interested candidates can DM me directly on LinkedIn or share their updated resume at nagu.ms@leadicdesign.com.
Show more Show less