LS
Senior Physical Design Engineer
Accepting applicationsL&T Semiconductor Technologies · Bengaluru, Karnataka, India
Full-Time Mid_senior RTL2GDSFloorplanPlacementCTSSTA
Estimated market salary
₹20-36 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
4d ago
Category
Design
Experience
Mid_senior
Country
India
Purpose:
As a Senior SoC Physical Design Implementation, the role includes working on the SoC/Subsystem level RTL2GDS Implementation with aligned PPA & Power/DRC Signoff as per PDK requirements. The role also oversee the Implementation strategy with Signoff Analysis, Timing/LV/EM/IR Analysis/ESD Analysis with driving methodology and commanding tools with flow. Collaboration as partner with Frontend and Packaging Teams/Full Chip Integration Teams. This position involves technical expertise and problem-solving skills to manage the estimation and project effectively.
Experience: 6 to 11 years
Responsibilities:
Leadership:
Manage the Physical Design of Top/SS/Partitions, ensuring alignment with the overall project and company objectives.
Mentor and develop team members, fostering a culture of excellence, collaboration, and continuous learning.
Coordinate cross-functional teams including RTL designers, verification engineers, and post-silicon teams to ensure seamless sign-off processes.
2 Physical Design Integration & Implementation:
Develop and implementation strategies that ensure the quality and reliability of physical designs.
Establish and enforce methodologies, best practices, and checklists for BE Integration/PNR/Floor Plan/Power Mesh/Clocking/Power integrity, Signal Integrity, Timing Signoff DRC/LVS clean-up, and other sign-off criteria.
Adoption of the latest tools, technologies, and methodologies to improve sign-off efficiency and effectiveness.
3 Technical Oversight:
Provide expert guidance in resolving complex sign-off issues related to PNR, and timing/physical verification.
Analyze and resolve any bottlenecks in the physical design process, ensuring design meets all performance, area, and power requirements.
Collaborate closely with the design and verification teams to ensure that the physical design is sign-off ready.
Collaboration with EDA:
Collaborate EDA tool vendors, ensuring the company’s needs are met about tool features, enhancements, and support.
Evaluate and recommend new tools and methodologies for physical design and sign-off.
5 Quality:
Ensure that all designs meet the required quality standards before sign-off, including thorough verification of timing, power, and physical integrity. Implement robust quality control measures to ensure zero-defect silicon and first-time-right success.
6 Compliance and Standards:
Ensure compliance with industry standards and regulatory requirements during the sign-off process.
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As a Senior SoC Physical Design Implementation, the role includes working on the SoC/Subsystem level RTL2GDS Implementation with aligned PPA & Power/DRC Signoff as per PDK requirements. The role also oversee the Implementation strategy with Signoff Analysis, Timing/LV/EM/IR Analysis/ESD Analysis with driving methodology and commanding tools with flow. Collaboration as partner with Frontend and Packaging Teams/Full Chip Integration Teams. This position involves technical expertise and problem-solving skills to manage the estimation and project effectively.
Experience: 6 to 11 years
Responsibilities:
Leadership:
Manage the Physical Design of Top/SS/Partitions, ensuring alignment with the overall project and company objectives.
Mentor and develop team members, fostering a culture of excellence, collaboration, and continuous learning.
Coordinate cross-functional teams including RTL designers, verification engineers, and post-silicon teams to ensure seamless sign-off processes.
2 Physical Design Integration & Implementation:
Develop and implementation strategies that ensure the quality and reliability of physical designs.
Establish and enforce methodologies, best practices, and checklists for BE Integration/PNR/Floor Plan/Power Mesh/Clocking/Power integrity, Signal Integrity, Timing Signoff DRC/LVS clean-up, and other sign-off criteria.
Adoption of the latest tools, technologies, and methodologies to improve sign-off efficiency and effectiveness.
3 Technical Oversight:
Provide expert guidance in resolving complex sign-off issues related to PNR, and timing/physical verification.
Analyze and resolve any bottlenecks in the physical design process, ensuring design meets all performance, area, and power requirements.
Collaborate closely with the design and verification teams to ensure that the physical design is sign-off ready.
Collaboration with EDA:
Collaborate EDA tool vendors, ensuring the company’s needs are met about tool features, enhancements, and support.
Evaluate and recommend new tools and methodologies for physical design and sign-off.
5 Quality:
Ensure that all designs meet the required quality standards before sign-off, including thorough verification of timing, power, and physical integrity. Implement robust quality control measures to ensure zero-defect silicon and first-time-right success.
6 Compliance and Standards:
Ensure compliance with industry standards and regulatory requirements during the sign-off process.
Show more Show less