HT
Senior Physical Design Engineer
Accepting applicationsHighbrow Technology Inc · San Francisco Bay Area
Full-Time Mid_senior ASICCalibreGenusInnovusPerl
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
United States
About the Role
Develop and own physical design implementation of multi-hierarchy low-power and high-performance designs, including physical-aware logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical verification in advanced technology nodes.
Responsibilities
Resolve design and flow issues related to the physical design, identify potential solutions, and drive execution.
Deliver physical design of an end-to-end IP or integration of ASIC/SoC design and point out lower power and higher performance trade-offs.
Define and implement schemes, including semi-custom placement and routing, to improve performance and power.
Work with the RTL design team to understand partition architecture and drive physical aspects early in the design cycle.
Interface with the RTL design team to drive design modifications to resolve congestion/timing issues and implement functional ECO's.
Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality.
Interact with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new vendor tools and functions.
Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
8+ years of experience in physical design and timing closure.
Knowledge of RTL2GDSII flow and design tape-outs in 5nm or below process technologies.
Experience with EDA tools like DC/Genus, Innovus/ICC2, Primetime, Redhawk/Voltus, or Calibre.
Hands-on experience in SoC floor planning, place & route, power and clock distribution, and timing convergence of high-frequency designs.
Knowledge of geometry/process/device technology implications on physical design.
Experience with large SOC designs (>100M gates) with frequencies over 1GHZ.
Experience collaborating effectively with both internal and external teams across various functions and geographic locations.
Programming/scripting skills: TCL, Python, Perl or Shell.
Required Skills
Physical design implementation.
Low-power and high-performance designs.
EDA tool-based programming and scripting.
Preferred Skills
Experience with large SOC designs.
Collaboration with internal and external teams.
Show more Show less
Develop and own physical design implementation of multi-hierarchy low-power and high-performance designs, including physical-aware logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical verification in advanced technology nodes.
Responsibilities
Resolve design and flow issues related to the physical design, identify potential solutions, and drive execution.
Deliver physical design of an end-to-end IP or integration of ASIC/SoC design and point out lower power and higher performance trade-offs.
Define and implement schemes, including semi-custom placement and routing, to improve performance and power.
Work with the RTL design team to understand partition architecture and drive physical aspects early in the design cycle.
Interface with the RTL design team to drive design modifications to resolve congestion/timing issues and implement functional ECO's.
Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality.
Interact with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new vendor tools and functions.
Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
8+ years of experience in physical design and timing closure.
Knowledge of RTL2GDSII flow and design tape-outs in 5nm or below process technologies.
Experience with EDA tools like DC/Genus, Innovus/ICC2, Primetime, Redhawk/Voltus, or Calibre.
Hands-on experience in SoC floor planning, place & route, power and clock distribution, and timing convergence of high-frequency designs.
Knowledge of geometry/process/device technology implications on physical design.
Experience with large SOC designs (>100M gates) with frequencies over 1GHZ.
Experience collaborating effectively with both internal and external teams across various functions and geographic locations.
Programming/scripting skills: TCL, Python, Perl or Shell.
Required Skills
Physical design implementation.
Low-power and high-performance designs.
EDA tool-based programming and scripting.
Preferred Skills
Experience with large SOC designs.
Collaboration with internal and external teams.
Show more Show less