Senior Physical Design Engineer

Greetings of the day!!!


We are planning for a scheduled Weekend drive for 5+ years Physical Design Engineers, if you are available this weekend or any references plz check and share this inf

o
Exp: 5 Yea
rsWork Location: Bangalore & Hyderab
adDate: 27th June 2026 (Bangalore) & 4th July 2026 (Hyderaba
d)Drive location: HCL Technologies (Sankalp Semiconductor) 4th Floor, 401E – B Wing (East) Campus 1, RMZ- Ecoworld SEZ 20&21, Deverabeesanahalli, Bellandur Bengaluru – 5601
03SPOC: Prade

ep
Interested candidates or referrals can share their resumes at vijay.kaki@hcltech.com once shortlisted will share invite lett

ers
About the Com
panyHCLTech is committed to innovation and excellence in technology services, fostering a culture of collaboration and gro

wth.
Job Sum
mary:We are seeking an experienced Senior Physical Design Engineer with over 5 years of expertise in VLSI chip design and implementation. The ideal candidate will have a strong background in RTL-to-GDSII flow, SOC/block-level physical design, and tapeout experience in advanced technology nodes (7nm, 5nm, or below). This role involves leading physical design projects, mentoring junior engineers, and collaborating closely with cross-functional teams including RTL design, DFT, timing, and packaging t
eams.In the semiconductor and VLSI (Very Large Scale Integration) industry, PNR, STA, EMIR and VCLP are core components of the Physical Design Engineer or Back-end Design job description. These roles focus on transforming a logical design (netlist) into a physical layout ready for manufactu


ring.

PNR (Place and
Route):Definition: The process of placing electronic components (macros and standard cells) and defining the wiring (routing) betwe
en them.Responsibilities: Includes floorplanning, power planning, clock tree synthesis (CTS), and routing to meet Performance, Power, and Area (PPA)
targets.Common Tools: Synopsys Fusion Compiler, Cadence Innovus, a

n
d ICC2
.STA (Static Timing An
alysis):Definition: A method of validating the timing performance of a design by checking all possible paths for timing violations without simulating the full
circuit.Responsibilities: Identifying and fixing setup and hold time violations to ensure the chip runs at its target fr
equency.Common Tools: Synopsys PrimeTime and Cadence

Tempus.
VCLP (Voltage-aware Check for Lo
w Power):Definition: A signoff check used to verify the integrity of low-power designs, specifically those using Unified Power Form
at (UPF).Responsibilities: Checking for electrical rule violations related to multiple power domains, such as missing isolation cells or level
shiftersCommon Tool: Syno

psys VCLP
Typical RequirementsScripting: Proficiency in Tcl, Perl, or Python for automating d

esign flow
Pay range and compensat
ion packageDetails regarding pay range or salary will be discussed during the intervi

ew process.
Equal Opportuni
ty StatementHCLTech is an equal opportunity employer and is committed to fostering a diverse and inclusiv

e workplace.
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