FR
Senior Physical Design Engineer
Accepting applicationsF. Robin Technologies | A Division of F. Robin Group · Karnataka, India
Contract Mid_senior CadenceCalibreDFTFinFETInnovus
Estimated market salary
₹20-36 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
21h ago
Category
Design
Experience
Mid_senior
Country
India
Job Summary: Seeking an experienced Physical Design Engineer to independently own and drive end-to-end implementation of complex IPs and subsystems from netlist handoff through tapeout. The role requires strong expertise in advanced-node physical design, signoff closure, and technical leadership to meet aggressive PPA and schedule targets.
Key Responsibilities:
• Own complete physical design flow for complex IPs/subsystems from floorplan to GDSII.
• Drive Floorplanning, Power Planning, Placement, CTS, Routing, Timing Closure, and Signoff.
• Achieve timing, power, area, congestion, IR/EM, and physical verification closure.
• Lead implementation reviews and collaborate with RTL, STA, DFT, and SoC teams.
• Debug and resolve design, tool, and methodology challenges.
• Support tapeout activities and ensure high-quality deliverables.
• Mentor junior engineers and drive methodology improvements.
Required Skills:
• Strong hands-on experience in Floorplanning & Power Planning, Placement & Optimization, CTS, MCMM Timing Closure, Signal Integrity, IR Drop & EM Analysis, and DRC/LVS Signoff Closure.
• Expertise in Cadence Innovus and/or Synopsys ICC2.
• Strong knowledge of PrimeTime/Tempus, Voltus/RedHawk, and Calibre.
• Experience in 7nm/5nm/3nm FinFET technologies.
• Proficiency in TCL, Perl, Python, or Shell scripting.
Intel 18A experience will be a plus
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Key Responsibilities:
• Own complete physical design flow for complex IPs/subsystems from floorplan to GDSII.
• Drive Floorplanning, Power Planning, Placement, CTS, Routing, Timing Closure, and Signoff.
• Achieve timing, power, area, congestion, IR/EM, and physical verification closure.
• Lead implementation reviews and collaborate with RTL, STA, DFT, and SoC teams.
• Debug and resolve design, tool, and methodology challenges.
• Support tapeout activities and ensure high-quality deliverables.
• Mentor junior engineers and drive methodology improvements.
Required Skills:
• Strong hands-on experience in Floorplanning & Power Planning, Placement & Optimization, CTS, MCMM Timing Closure, Signal Integrity, IR Drop & EM Analysis, and DRC/LVS Signoff Closure.
• Expertise in Cadence Innovus and/or Synopsys ICC2.
• Strong knowledge of PrimeTime/Tempus, Voltus/RedHawk, and Calibre.
• Experience in 7nm/5nm/3nm FinFET technologies.
• Proficiency in TCL, Perl, Python, or Shell scripting.
Intel 18A experience will be a plus
Show more Show less