Senior Physical Design Engineer

Job Opening: Physical Design Engineer (5+ Years)
Location: Bangalore/Hyderabad/Chennai/Pune/Noida/Ahmedabad
Experience Required: 4+ Years
Company: eInfochips

Employment Type: Full-time
🚀 Job Responsibilities:
Perform block-level and full-chip physical design activities.
Handle floorplanning, placement, CTS, routing, and timing closure.
Work on physical verification including DRC, LVS, and ERC checks.
Perform STA analysis and support timing closure across corners and modes.
Handle IR drop analysis, power planning, and EM checks.
Debug and resolve physical design issues related to congestion, timing, and power.
Collaborate closely with RTL, DFT, and STA teams for design closure.
Ensure delivery of high-quality layouts meeting PPA (Power, Performance, Area) targets.
🛠 Required Skills:
Strong hands-on experience in physical design flow from netlist to GDSII.
Expertise in floorplanning, placement, CTS, routing, and signoff checks.
Experience with tools like:
Cadence Innovus
Synopsys ICC2
PrimeTime
Calibre (DRC/LVS)
Good understanding of:
Timing closure
Signal integrity
Low-power concepts
MMMC setup
Experience working on advanced technology nodes is preferred.
✅ Preferred Qualifications:
Bachelor’s or Master’s degree in Electronics / VLSI / ECE.
Strong debugging and problem-solving skills.
Good communication and teamwork abilities.

📩 How to Apply:
Interested candidates can share their updated resume at:
Nshalini.singh@einfochips.com
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