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Senior Physical Design Engineer
Accepting applicationsBITSILICA · Bengaluru, Karnataka, India
Full-Time Mid_senior CadenceCalibreDFTInnovusPerl
Estimated market salary
₹14-25 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
2d ago
Category
Design
Experience
Mid_senior
Country
India
About the Company
As a Senior Physical Design Engineer, you will be responsible for the end-to-end implementation of complex SoCs at advanced process nodes (e.g., 7nm, 5nm, and below). You will work closely with the synthesis, STA, and DFT teams to deliver high-quality GDSII, ensuring all PPA (Power, Performance, Area) targets are met.
Responsibilitie
sNetlist-to-GDSII Flow: Execute the complete physical design flow, including Floorplanning, Placement, Clock Tree Synthesis (CTS), and Routing
.Timing Closure: Perform Static Timing Analysis (STA) and timing closure across all corners and modes (setup, hold, recovery, removal)
.Physical Verification: Own and resolve DRC, LVS, ERC, and Antenna violations using industry-standard tools
.Power Analysis: Conduct IR drop analysis (Static and Dynamic) and EM (Electromigration) analysis to ensure robust power delivery
.Optimization: Implement area reduction techniques and low-power design methodologies (UPF/CPF)
.Collaboration: Interface with the RTL and DFT teams to resolve design hurdles and provide feedback on physical constraints
.
Qualificatio
nsBachelor’s or Master’s degree in Electrical/Electronics Engineering or a related fiel
d.
Required Ski
llsEDA Tools: Proficiency in industry-leading tools such as Innovus (Cadence) or ICC2 (Synopsy
s).Verification Tools: Hands-on experience with Calibre, Assura, or I
CV.Methodology: Strong understanding of hierarchical design, multi-voltage domains, and congestion manageme
nt.Nodes: Experience working on advanced process nodes (7nm/5nm/3n
m).Scripting: Ability to automate tasks using Tcl, Perl, or Pyth
on.
Preferred Sk
illsStrong analytical and problem-solving ski
lls.Excellent communication skills for cross-functional team coordinat
ion.
Show more Show less
As a Senior Physical Design Engineer, you will be responsible for the end-to-end implementation of complex SoCs at advanced process nodes (e.g., 7nm, 5nm, and below). You will work closely with the synthesis, STA, and DFT teams to deliver high-quality GDSII, ensuring all PPA (Power, Performance, Area) targets are met.
Responsibilitie
sNetlist-to-GDSII Flow: Execute the complete physical design flow, including Floorplanning, Placement, Clock Tree Synthesis (CTS), and Routing
.Timing Closure: Perform Static Timing Analysis (STA) and timing closure across all corners and modes (setup, hold, recovery, removal)
.Physical Verification: Own and resolve DRC, LVS, ERC, and Antenna violations using industry-standard tools
.Power Analysis: Conduct IR drop analysis (Static and Dynamic) and EM (Electromigration) analysis to ensure robust power delivery
.Optimization: Implement area reduction techniques and low-power design methodologies (UPF/CPF)
.Collaboration: Interface with the RTL and DFT teams to resolve design hurdles and provide feedback on physical constraints
.
Qualificatio
nsBachelor’s or Master’s degree in Electrical/Electronics Engineering or a related fiel
d.
Required Ski
llsEDA Tools: Proficiency in industry-leading tools such as Innovus (Cadence) or ICC2 (Synopsy
s).Verification Tools: Hands-on experience with Calibre, Assura, or I
CV.Methodology: Strong understanding of hierarchical design, multi-voltage domains, and congestion manageme
nt.Nodes: Experience working on advanced process nodes (7nm/5nm/3n
m).Scripting: Ability to automate tasks using Tcl, Perl, or Pyth
on.
Preferred Sk
illsStrong analytical and problem-solving ski
lls.Excellent communication skills for cross-functional team coordinat
ion.
Show more Show less