LT
Senior Physical Design Engineer, (5+Exp)
Accepting applicationsLyptus Technologies · Bengaluru South, Karnataka, India
Full-Time Mid_senior ASICCadenceDFTPerlPython
Estimated market salary
₹20-36 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
22h ago
Category
Design
Experience
Mid_senior
Country
India
Company Description Lyptus Technologies delivers cutting-edge, end-to-end solutions spanning silicon design, test, hardware, base software, applications, and support. The company provides semiconductor solution development across multiple verticals, enabling clients to bring complex products to market efficiently. Core expertise includes front-end design and verification, formal verification, DFT, physical design, and static timing analysis (STA). Lyptus also specializes in platform engineering for RTOS, Linux, and BIOS, along with digital engineering, machine learning, and DSP, offering a broad technical environment for engineering professionals.
Role Description The Senior Physical Design Engineer (5+ years of experience) will be responsible for driving block- and chip-level physical design activities, including floorplanning, placement, clock tree synthesis, routing, and timing closure. Day-to-day work involves collaborating with RTL, logic, and verification teams to ensure robust implementation, performing physical verification and sign-off checks, and optimizing power, performance, and area. The engineer will analyze and resolve design, congestion, and timing issues, prepare documentation, and contribute to design flows and methodology improvements. This is a full-time, on-site role based in Bengaluru South, requiring close coordination with cross-functional teams and active participation in project planning and reviews.
Qualifications
Strong expertise in Physical Design, including floorplanning, placement, clock tree synthesis, routing, and timing closure.
Proficiency in Physical Verification, including DRC, LVS, IR drop, EM analysis, and sign-off flows.
Solid understanding of Logic Design and Circuit Design fundamentals for digital integrated circuits.
Experience with RTL Design, including interpreting and working closely with RTL for implementation and optimization.
5+ years of relevant industry experience in ASIC/SoC physical design and implementation.
Hands-on experience with industry-standard EDA tools (e.g., Synopsys, Cadence) and scripting (e.g., Python, Perl, Tcl) to automate flows.
Knowledge of STA concepts, low-power design techniques, and design-for-test (DFT) considerations.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field.
Effective communication, problem-solving, and collaboration skills, with the ability to work in a fast-paced, team-oriented environment.
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Role Description The Senior Physical Design Engineer (5+ years of experience) will be responsible for driving block- and chip-level physical design activities, including floorplanning, placement, clock tree synthesis, routing, and timing closure. Day-to-day work involves collaborating with RTL, logic, and verification teams to ensure robust implementation, performing physical verification and sign-off checks, and optimizing power, performance, and area. The engineer will analyze and resolve design, congestion, and timing issues, prepare documentation, and contribute to design flows and methodology improvements. This is a full-time, on-site role based in Bengaluru South, requiring close coordination with cross-functional teams and active participation in project planning and reviews.
Qualifications
Strong expertise in Physical Design, including floorplanning, placement, clock tree synthesis, routing, and timing closure.
Proficiency in Physical Verification, including DRC, LVS, IR drop, EM analysis, and sign-off flows.
Solid understanding of Logic Design and Circuit Design fundamentals for digital integrated circuits.
Experience with RTL Design, including interpreting and working closely with RTL for implementation and optimization.
5+ years of relevant industry experience in ASIC/SoC physical design and implementation.
Hands-on experience with industry-standard EDA tools (e.g., Synopsys, Cadence) and scripting (e.g., Python, Perl, Tcl) to automate flows.
Knowledge of STA concepts, low-power design techniques, and design-for-test (DFT) considerations.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field.
Effective communication, problem-solving, and collaboration skills, with the ability to work in a fast-paced, team-oriented environment.
Show more Show less
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