RI
Senior Mixed-Signal Verification Engineer
Accepting applicationsRetym, Inc · Austin, Texas Metropolitan Area
Full-Time Mid_senior AIAnalogCadenceMixed SignalMixed-Signal
Posted
28 May
Category
Design
Experience
Mid_senior
Country
United States
Retym is revolutionizing AI infrastructure and cloud connectivity with groundbreaking digital signal processing (DSP) innovations. Our state-of-the-art technologies are engineered to maximize AI performance, minimize latency, and deliver effortless scalability for next-generation applications.
At Retym, we bring together world-class experts in analog, DSP, VLSI, and optical communications, and collaborate with visionary investors to redefine the landscape of AI infrastructure.
With headquarters in Silicon Valley and offices in Austin, Tel Aviv, and Yerevan, Retym is rapidly expanding. We are looking for passionate, driven individuals to join our dynamic team and help shape the future of AI technology.
Become part of a collaborative, forward-thinking environment where your work will make a real impact.
About The Position
For an exciting, well-funded start-up, developing leading-edge technology for the next generation of high-speed communication, we are looking for a Mixed-signal verification engineer.
Requirements
Key Responsibilities:
Develop verification strategies for digital and analog (mixed-signal) designs, utilizing UVM methodologies based on specifications.
Create behavioral models for analog blocks in accordance with the guidelines provided by analog designers.
Write, execute, and debug testbenches using UVM methodology and SystemVerilog code for mixed-signal blocks.
Run and debug the behavioral model (BM) validation using AMS tools to ensure the correctness of the behavioral models.
Perform and troubleshoot unit-level, cluster-level, and top-level simulations of mixed-signal designs.
Minimum Qualifications
5+ years of experience
Experience in Behavioral Modeling (BM) of Analog design for digital verification
Knowledge in Mixed Signals dynamic Verification using chip digital design tools [no AMS]
Experience in Verilog/SystemVerilog coding
Experience in Virtuoso Schematics tools
Basic knowledge in Analog design
Preferred Qualifications
Experience in UVM
Experience in both Synopsys and Cadence tools is an advantage
Additional Skills
Verification Methodologies and Tools: Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases.
Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative team environment.
Communication: Strong communication skills, including the ability to write test plans, present results, and communicate clearly with multi-functional teams.
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At Retym, we bring together world-class experts in analog, DSP, VLSI, and optical communications, and collaborate with visionary investors to redefine the landscape of AI infrastructure.
With headquarters in Silicon Valley and offices in Austin, Tel Aviv, and Yerevan, Retym is rapidly expanding. We are looking for passionate, driven individuals to join our dynamic team and help shape the future of AI technology.
Become part of a collaborative, forward-thinking environment where your work will make a real impact.
About The Position
For an exciting, well-funded start-up, developing leading-edge technology for the next generation of high-speed communication, we are looking for a Mixed-signal verification engineer.
Requirements
Key Responsibilities:
Develop verification strategies for digital and analog (mixed-signal) designs, utilizing UVM methodologies based on specifications.
Create behavioral models for analog blocks in accordance with the guidelines provided by analog designers.
Write, execute, and debug testbenches using UVM methodology and SystemVerilog code for mixed-signal blocks.
Run and debug the behavioral model (BM) validation using AMS tools to ensure the correctness of the behavioral models.
Perform and troubleshoot unit-level, cluster-level, and top-level simulations of mixed-signal designs.
Minimum Qualifications
5+ years of experience
Experience in Behavioral Modeling (BM) of Analog design for digital verification
Knowledge in Mixed Signals dynamic Verification using chip digital design tools [no AMS]
Experience in Verilog/SystemVerilog coding
Experience in Virtuoso Schematics tools
Basic knowledge in Analog design
Preferred Qualifications
Experience in UVM
Experience in both Synopsys and Cadence tools is an advantage
Additional Skills
Verification Methodologies and Tools: Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases.
Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative team environment.
Communication: Strong communication skills, including the ability to write test plans, present results, and communicate clearly with multi-functional teams.
Show more Show less