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Senior Memory Circuit Design Engineer
Accepting applicationsBroadcom · Bengaluru, Karnataka, India
Full-Time Mid_senior DFT
Estimated market salary
₹24-44 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
1d ago
Category
Test
Experience
Mid_senior
Country
India
Job Description:
Analyze different memory architectures and highlight the tradeoffs
Design and build memory or circuit blocks at the gate or transistor level
Simulate and analyze the circuit design using transistor level simulators
Extract the layout and perform post-layout simulations and verification
Floorplan physical implementation and leafcell layout integration to build the physical macro
Integrate characterization flow to extract timing and power information
Develop scripts to automate characterization flow, simulations, and verification
Specify and verify various behavioral and physical memory models
Document the design specifications, behavioral description, and timing diagrams
Specify silicon test plan and correlate silicon to simulation data
Help debug silicon issues
Skillset Required
Knowledge in development of memory compilers or custom digital circuits of all types; SRAMs, Register-files, Multi-ports, ROM, etc…
Good understanding of transistor level circuit behavior and device physics
Good understanding of signal integrity, EM/IR, and reliability analysis
Understanding of memory behavioral and physical models
Understanding of DFT schemes and chip level integration
Familiarity with test setups, silicon testing and debug is a plus
Proficient in running simulators, writing automation scripts, and are tools savvy
Good communication, interpersonal, and leadership skills
Motivated, self-driven and good at multi-tasking
R026827
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Analyze different memory architectures and highlight the tradeoffs
Design and build memory or circuit blocks at the gate or transistor level
Simulate and analyze the circuit design using transistor level simulators
Extract the layout and perform post-layout simulations and verification
Floorplan physical implementation and leafcell layout integration to build the physical macro
Integrate characterization flow to extract timing and power information
Develop scripts to automate characterization flow, simulations, and verification
Specify and verify various behavioral and physical memory models
Document the design specifications, behavioral description, and timing diagrams
Specify silicon test plan and correlate silicon to simulation data
Help debug silicon issues
Skillset Required
Knowledge in development of memory compilers or custom digital circuits of all types; SRAMs, Register-files, Multi-ports, ROM, etc…
Good understanding of transistor level circuit behavior and device physics
Good understanding of signal integrity, EM/IR, and reliability analysis
Understanding of memory behavioral and physical models
Understanding of DFT schemes and chip level integration
Familiarity with test setups, silicon testing and debug is a plus
Proficient in running simulators, writing automation scripts, and are tools savvy
Good communication, interpersonal, and leadership skills
Motivated, self-driven and good at multi-tasking
R026827
Show more Show less