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Senior Lead Memory Circuit Design Engineer
Accepting applicationsW3Global · Sunnyvale, CA
Full-Time Principal AnalogCadenceMentorMixed-SignalSPICE
Posted
22h ago
Category
Verification
Experience
Principal
Country
United States
Senior Lead Memory Circuit Design Engineer - Mixed-Signal / NVM
Location: Mesa, AZ (preferred; CA candidates considered)
Role
Lead end-to-end memory subsystem design from architecture through tapeout for advanced mixed-signal SoCs, collaborating with Analog, Digital, Verification, and Layout teams.
Key Responsibilities
Own memory architecture, circuit design, verification, signoff, and tapeout.
Design/optimize memory arrays, sense amplifiers, references, read/write circuits, decoders, and datapaths.
Perform SPICE simulations, PVT/temperature sweeps, Monte Carlo, mismatch, and reliability analysis.
Review chip-level timing issues, margins, waveforms, and signoff results.
Partner with Layout on floorplanning, parasitics, EM/IR, density, antenna, and signoff.
Mentor engineers and lead cross-functional execution.
Required Qualifications
BSEE/MSEE/PhD or equivalent.
15+ years of memory circuit design experience, including SRAM and NVM.
Multiple successful tapeouts with subsystem/block ownership.
Strong mixed-signal, sense amplifier, reference generation, and memory architecture expertise.
Experience with Cadence/Synopsys and SPICE tools such as HSPICE, Spectre, or PrimeSim.
Strong leadership and mentoring skills.
Preferred
MRAM/RRAM or other resistive/NVM experience.
Silicon characterization and post-silicon debug.
Crosspoint-style memory architectures.
EM/IR, ESD, latch-up, and reliability signoff experience.
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Location: Mesa, AZ (preferred; CA candidates considered)
Role
Lead end-to-end memory subsystem design from architecture through tapeout for advanced mixed-signal SoCs, collaborating with Analog, Digital, Verification, and Layout teams.
Key Responsibilities
Own memory architecture, circuit design, verification, signoff, and tapeout.
Design/optimize memory arrays, sense amplifiers, references, read/write circuits, decoders, and datapaths.
Perform SPICE simulations, PVT/temperature sweeps, Monte Carlo, mismatch, and reliability analysis.
Review chip-level timing issues, margins, waveforms, and signoff results.
Partner with Layout on floorplanning, parasitics, EM/IR, density, antenna, and signoff.
Mentor engineers and lead cross-functional execution.
Required Qualifications
BSEE/MSEE/PhD or equivalent.
15+ years of memory circuit design experience, including SRAM and NVM.
Multiple successful tapeouts with subsystem/block ownership.
Strong mixed-signal, sense amplifier, reference generation, and memory architecture expertise.
Experience with Cadence/Synopsys and SPICE tools such as HSPICE, Spectre, or PrimeSim.
Strong leadership and mentoring skills.
Preferred
MRAM/RRAM or other resistive/NVM experience.
Silicon characterization and post-silicon debug.
Crosspoint-style memory architectures.
EM/IR, ESD, latch-up, and reliability signoff experience.
Show more Show less