SS
Senior Lead/Lead Engineer- ASIC verification
Accepting applicationsSignOff Semiconductors · Bengaluru South, Karnataka, India
Other Mid_senior ASICC++DDREthernetFPGA
Estimated market salary
₹24-44 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
3d ago
Category
Verification
Experience
Mid_senior
Country
India
Exp: 8+Yrs
Location: Bangalore
Notice Period: Immediate to 30 days
Key Responsibilities
Lead ASIC/SoC/IP verification activities.
Define verification plans, methodologies, and sign-off criteria.
Develop and review UVM/SystemVerilog-based verification environments.
Drive verification execution, debug, regression, and coverage closure.
Collaborate with customers and internal stakeholders.
Mentor and guide verification engineers.
Ensure quality delivery within project timelines.
Requirements
Required Technical Skills
(1)The ideal candidate should have strong experience in ASIC/SoC/IP Functional Verification with hands-on expertise in SystemVerilog and UVM.
(2)Experience in developing verification environments, test benches, sequences, scoreboards, monitors, drivers, and functional coverage models is essential.
(3)Candidates should possess a strong understanding of constrained-random and coverage-driven verification methodologies, along with experience in simulation, debugging, regression, coverage analysis, verification planning, and sign-off.
(4)A solid foundation in RTL design and digital logic is required. Experience with protocols such as AMBA AXI/AHB/APB, PCIe, Ethernet, USB, or DDR is preferred.
(5)Knowledge of Python, Perl, or C/C++, and exposure to Formal Verification, Emulation, FPGA Prototyping, or Post-Silicon Validation will be an added advantage.
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Location: Bangalore
Notice Period: Immediate to 30 days
Key Responsibilities
Lead ASIC/SoC/IP verification activities.
Define verification plans, methodologies, and sign-off criteria.
Develop and review UVM/SystemVerilog-based verification environments.
Drive verification execution, debug, regression, and coverage closure.
Collaborate with customers and internal stakeholders.
Mentor and guide verification engineers.
Ensure quality delivery within project timelines.
Requirements
Required Technical Skills
(1)The ideal candidate should have strong experience in ASIC/SoC/IP Functional Verification with hands-on expertise in SystemVerilog and UVM.
(2)Experience in developing verification environments, test benches, sequences, scoreboards, monitors, drivers, and functional coverage models is essential.
(3)Candidates should possess a strong understanding of constrained-random and coverage-driven verification methodologies, along with experience in simulation, debugging, regression, coverage analysis, verification planning, and sign-off.
(4)A solid foundation in RTL design and digital logic is required. Experience with protocols such as AMBA AXI/AHB/APB, PCIe, Ethernet, USB, or DDR is preferred.
(5)Knowledge of Python, Perl, or C/C++, and exposure to Formal Verification, Emulation, FPGA Prototyping, or Post-Silicon Validation will be an added advantage.
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