IR
Senior Hardware Design Engineer
Accepting applicationsIC Resources · Irvine, CA
Full-Time Mid_senior ASICC++FPGAPythonRTL
Posted
21h ago
Category
Design
Experience
Mid_senior
Country
United States
We're hiring: Senior Hardware Design Engineer (Irvine, CA, Hybrid)
Work on technology at the leading edge of non terrestrial communications, a 5G base station built to be deployed on board satellites.
This is deep tech with real world impact: baseband signal processing IP that's already proven in orbit, powering hundreds of operational satellite communications systems worldwide.
What you'll work on:
Space qualified devices, delivering standalone and integrated IP solutions
RTL implementation (Verilog/SystemVerilog) for complex ASIC/FPGA products
Full design flow collaboration: micro architecture, design, verification, physical implementation and optimization
What we're looking for:
Expert level RTL design experience in ASIC and FPGA
Strong track record in timing and hardware resource optimization
Experience with EDA tools for simulation and synthesis
Bonus points for UVM, C++/SystemC, high speed interfaces (PCI E, JESD), or Python
If you want to work on technology that's shaping the future of global connectivity from orbit, not just talk about it, this is a rare seat.
Permanent, hybrid, Irvine, CA.
Interested or know someone who'd be a fit? Send a message or drop a note below.
Show more Show less
Work on technology at the leading edge of non terrestrial communications, a 5G base station built to be deployed on board satellites.
This is deep tech with real world impact: baseband signal processing IP that's already proven in orbit, powering hundreds of operational satellite communications systems worldwide.
What you'll work on:
Space qualified devices, delivering standalone and integrated IP solutions
RTL implementation (Verilog/SystemVerilog) for complex ASIC/FPGA products
Full design flow collaboration: micro architecture, design, verification, physical implementation and optimization
What we're looking for:
Expert level RTL design experience in ASIC and FPGA
Strong track record in timing and hardware resource optimization
Experience with EDA tools for simulation and synthesis
Bonus points for UVM, C++/SystemC, high speed interfaces (PCI E, JESD), or Python
If you want to work on technology that's shaping the future of global connectivity from orbit, not just talk about it, this is a rare seat.
Permanent, hybrid, Irvine, CA.
Interested or know someone who'd be a fit? Send a message or drop a note below.
Show more Show less
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