Senior FPGA Development Engineer

Summary

Job Summary

The Laboratory for Atmospheric and Space Physics (LASP) is seeking an FPGA Design Engineer IV to serve as a senior technical leader for flight digital logic used in spaceflight science instruments and spacecraft. This position is a principal individual-contributor and technical-lead role with responsibility for complex FPGA and adaptive system-on-chip (SoC) development across the full life cycle: requirements, architecture, RTL implementation, verification, hardware bring-up, environmental test, and instrument and spacecraft integration.

The Engineer IV will independently define technical approaches, own FPGA technical baselines, lead design and verification reviews, resolve high-consequence technical issues, and guide multidisciplinary teams from mission concept through flight delivery. The successful candidate will remain hands-on while mentoring engineers and students, establishing reusable practices, and advising program leadership on technical risk, cost, schedule, and readiness.

LASP's current flight portfolio spans planetary, lunar, heliophysics, and astrophysics missions: DAPHNE, a NASA heliophysics mission using twin satellites and UV imaging and spectroscopy to study how Earth's lower atmosphere drives its upper atmosphere; DUSTER, a dust and plasma instrument suite for a lunar rover on Artemis IV; EMA, an asteroid belt exploration spacecraft flown in partnership with the UAE Space Agency; and a continuing series of NASA-funded CubeSat missions. FPGA engineers at LASP move between mission classes rather than working a single program for a decade.

CU is an Equal Opportunity Employer and complies with all applicable federal, state, and local laws governing nondiscrimination in employment. We are committed to creating a workplace where all individuals are treated with respect and dignity, and we encourage individuals from all backgrounds to apply, including protected veterans and individuals with disabilities.

CU is an Equal Opportunity Employer and complies with all applicable federal, state, and local laws governing nondiscrimination in employment. We are committed to creating a workplace where all individuals are treated with respect and dignity, and we encourage individuals from all backgrounds to apply, including protected veterans and individuals with disabilities.

Who We Are

Founded a decade before NASA, the Laboratory for Atmospheric and Space Physics (LASP) at the University of Colorado Boulder is revolutionizing human understanding of the cosmos. LASP is deeply committed to inspiring and educating the next generation of space explorers. From enabling the first exploratory rocket measurements of Earth’s upper atmosphere to trailblazing observations of every planet in the solar system, LASP is at the forefront of solar, planetary and space physics research, space-weather monitoring, and the search for evidence of habitable worlds.

LASP advances scientific discovery and inspires the next generation through research, innovation, and education in space sciences. We employ over 700 scientists, engineers, support personnel, and students that work closely to cultivate creative ideas and explore novel solutions to make the impossible possible.

LASP is dedicated to building and maintaining a unique synergism of expertise in space science, engineering, and spacecraft operations. Through research projects, LASP participates actively in the training of the future leaders of space research and helps the University of Colorado to educate students with valued technical and scientific skills. Development and use of innovative technologies and continuing participation in new research initiatives ensures a strong leadership role for LASP into the future. LASP is proud of our work environment that supports employee creativity and productivity and offers opportunities for a broad range of experiences. Further information about LASP can be found here: https://lasp.colorado.edu/home/

Responsibilities

What Your Key Responsibilities Will Be

You may serve as the FPGA technical lead or lead architect for complex flight instruments and spacecraft, with accountability for the technical integrity and release readiness of assigned programmable-logic designs.
Translate mission and system objectives into FPGA architectures, derived requirements, interfaces, constraints, and verification strategies; allocate functions across FPGA fabric, embedded processors, software, and surrounding electronics.
Own and maintain the FPGA technical baseline, including requirements, architecture, RTL, intellectual property, constraints, verification evidence, release packages, and configuration-controlled design documentation.
Lead device-selection and architecture trade studies that balance capability, radiation tolerance, reliability, power, performance, resource utilization, thermal constraints, cost, schedule, supply-chain risk, and mission life.
Design and review complex FPGA and adaptive SoC logic in VHDL, Verilog, or SystemVerilog, from reusable blocks through full-device integration.
Define and lead verification and validation activities, including requirements-based test planning, independent review, simulation, coverage, static analysis, clock and reset domain crossing analysis, formal methods where appropriate, timing closure, and hardware-based verification.
Define radiation-tolerant and fault-management approaches, including SEU mitigation, error detection and correction, configuration scrubbing, fault containment, recovery, and the verification of mitigation effectiveness.
Participate in code, verification, and release-readiness reviews as either presenter or reviewer; document decisions and disposition technical risks, review actions, anomalies, nonconformances, and design changes.
Be hands-on through hardware bring-up, environmental testing, instrument and spacecraft integration, and complex failure investigations that may span programmable logic, electrical hardware, embedded software, interfaces, and test systems.
Collaborate with electrical, embedded software, systems, mechanical, science, and program-management teams on hardware and software co-design and mission-level technical decisions.
Represent LASP in technical exchanges and reviews with customers, partner institutions, vendors, and subcontractors; communicate recommendations, residual risks, and readiness to technical and program leadership.
Develop credible estimates and plans for FPGA work; identify dependencies, staffing needs, schedule drivers, and technical risks; track execution and provide clear status to program leadership.
Establish and improve design standards, reusable IP, review checklists, automation, lessons learned, and development practices that raise quality and productivity across the FPGA group.
Apply AI-assisted development tools to accelerate RTL, verification, scripting, and documentation while maintaining flight-quality rigor, independent review, disclosure, traceability, and configuration control of generated content.
Provide technical direction and mentorship to engineers and student employees, including delegation of well-defined work, constructive review, and development of technical judgment.
Other duties as assigned.

What You Should Know

Due to requirements to access export-controlled data and information, only U.S. citizens, lawful permanent residents (green card holders), or other protected individuals (i.e., persons designated as an asylee, refugee, or temporary resident under amnesty provisions) may apply.
This position requires onsite presence.
The role may require occasional travel to partner, vendor, environmental-test, integration, or launch facilities and occasional work outside normal business hours during critical test and integration activities.
The FPGA group uses AI-assisted development tools in daily work. We expect engineers to be comfortable with tool-assisted workflows and with the review, disclosure, and configuration-control practices that keep generated content traceable and flight-worthy.

What We Can Offer

$145,754.06-$189,585.27.

Benefits

At the University of Colorado Boulder , we are committed to supporting the holistic health and well-being of our employees. Our comprehensive benefits package includes medical, dental, and retirement plans; generous paid time off; tuition assistance for you and your dependents; and an ECO Pass for local transit. As one of Boulder County’s largest employers, CU Boulder offers an inspiring academic community and access to world-class outdoor recreation. Explore additional perks and programs through the CU Advantage program.

Be Statements

Be ambitious. Be groundbreaking. Be Boulder.

What We Require

Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or a closely related field from an accredited institution.
Demonstrated progressively responsible professional experience in FPGA, ASIC, or complex digital-logic development, including substantial hands-on FPGA design and roles requiring technical leadership.
Demonstrated technical ownership of at least one complex FPGA or adaptive SoC development through requirements, architecture, implementation, verification, hardware integration, and controlled release.
Expert proficiency in VHDL, Verilog, or SystemVerilog for synthesizable design, including the ability to review complex RTL and identify functional, timing, reset, interface, and maintainability risks.
Expertise with FPGA implementation flows, including synthesis, simulation, place and route, constraint development, static timing analysis, clock and reset domain crossing analysis, resource and power analysis, and timing closure.
Demonstrated experience developing against structured requirements and maintaining bidirectional traceability from requirements through implementation and verification evidence.
Experience defining and executing rigorous verification plans using simulation-based methods and appropriate combinations of coverage, linting, static analysis, assertions, or formal verification.
Experience applying design assurance, configuration management, independent review, and release-control practices in a high-reliability or mission-critical development environment.
Demonstrated experience leading technical reviews, resolving complex cross-disciplinary issues, and communicating technical decisions and risk to internal and external stakeholders.
Proficiency with engineering and project collaboration tools such as Git, Jira, Confluence, and requirements-management tools such as DOORS or an equivalent platform.
Proficiency in an electronics development laboratory and with relevant test equipment, including power supplies, oscilloscopes, function or signal generators, and logic analyzers.

What You Will Need

Independent judgment and the ability to establish a sound technical path when requirements are incomplete, risks are coupled, and no established solution exists.
Systems-level thinking and strong troubleshooting instincts when a fault may reside in the logic, board, embedded software, interface, test equipment, or requirements.
The ability to lead through technical influence, build consensus across disciplines, and make or recommend timely decisions while clearly documenting assumptions and residual risk.
Clear, concise written and verbal communication with engineers, scientists, managers, review boards, customers, and external partners.
The ability to plan and prioritize work across multiple programs, mentor less-experienced engineers, and provide constructive, technically rigorous review.
Skeptical review of design artifacts regardless of source, including inherited IP, vendor reference designs, third-party deliverables, and AI-generated code.
Documentation and configuration-control habits that support reproducibility, independent verification, anomaly resolution, and review-board scrutiny.

What We Would Like You To Have

Flight and radiation

Experience serving as FPGA technical lead or architect on one or more spaceflight, aerospace, or similarly high-consequence programs through qualification or operational deployment.
Deep knowledge of radiation effects and mitigation in FPGAs, including TMR, EDAC, scrubbing, fault injection, and single-event-effects analysis.
Experience applying and tailoring NASA or comparable programmable-logic design-assurance practices, such as NASA-HDBK-4008, across different mission-risk classifications.
Experience supporting failure modes and effects analysis, fault-tree analysis, independent verification, anomaly review, or flight-readiness review activities.

Devices, interfaces, and tools

Experience with AMD Versal, UltraScale+, or Zynq; Microchip PolarFire or PolarFire SoC; or Lattice Nexus device families.
Experience with SpaceWire, SpaceFibre, AXI, Ethernet, SPI, PCIe, JESD204, or LVDS source-synchronous interfaces.
Experience with external memory controllers and reliable memory architectures using DDR3 or DDR4, ONFI NAND, eMMC, MRAM, or similar technologies.
Advanced verification experience using UVM, cocotb, assertions, constrained-random testing, formal verification, or functional and code coverage.
Scripting and EDA automation in Python and Tcl, including reproducible builds, automated regression, metrics, and continuous-integration workflows.
Experience with hardware and software co-design, embedded processor integration, and bring-up of heterogeneous SoC platforms.

AI-assisted development

Experience using AI coding assistants and agentic development tools in a production RTL, verification, scripting, or documentation workflow, with sound judgment about suitable use cases and required independent review.
Experience automating design and EDA workflows through scripting and tool APIs, including AI-assisted generation or review of testbenches, constraints, register maps, requirements, or documentation.
Experience establishing reusable, secure, and reviewable AI-assisted workflows that improve engineering productivity without weakening technical accountability or configuration control.

Also useful

Experience implementing machine-learning inference, digital signal processing, compression, or other high-throughput algorithms in FPGA or adaptive SoC fabric for onboard data processing.
Experience with schematic capture, PCB design, high-speed digital signal integrity, and board-level design reviews.
Experience supporting proposals, basis-of-estimate development, supplier or subcontractor technical oversight, or the evaluation and acquisition of third-party IP.

Special Instructions

To Apply, Please Submit The Following Materials

Resume or CV.
Cover Letter.

(Optional) Transcripts/Proof of Degree: If you are selected as the finalist, your degree will be verified by the CU Boulder Campus Human Resources Department using an approved online vendor. However, if your degree was obtained outside of the United States, please submit an English-translated version as an Optional document.

Please apply by 8/18/2026 for consideration.

Note: Application materials will not be accepted via email. For consideration, applications must be submitted through CU Boulder Jobs.

In compliance with the Colorado Job Application Fairness Act, in any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.
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