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Senior FPGA Design Engineer
Accepting applicationsCyient · Melbourne, FL
Full-Time Mid_senior FPGAMATLABRFVHDL
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
United States
Job Summary
We are seeking a Senior FPGA/DSP Engineer with strong experience in VHDL, Xilinx FPGAs, and DSP algorithm implementation. The ideal candidate will have hands-on experience with FPGA development, hardware bring-up, debugging, and system integration.
Key Responsibilities
Implement DSP algorithms in FPGA hardware using VHDL.
Design, develop, verify, and document FPGA solutions.
Perform FPGA board bring-up, hardware debugging, and lab testing.
Conduct timing analysis and timing closure.
Support software and system integration/testing.
Participate in design reviews and technical documentation.
Required Skills
Strong VHDL/FPGA development experience.
Xilinx FPGA tools and architectures.
DSP, MATLAB modeling and simulation.
Linux development environment.
ModelSim/Questa experience.
FPGA hardware bring-up and debugging.
Timing analysis and closure.
Experience with RF, SDR, radar, or communications systems preferred.
Show more Show less
We are seeking a Senior FPGA/DSP Engineer with strong experience in VHDL, Xilinx FPGAs, and DSP algorithm implementation. The ideal candidate will have hands-on experience with FPGA development, hardware bring-up, debugging, and system integration.
Key Responsibilities
Implement DSP algorithms in FPGA hardware using VHDL.
Design, develop, verify, and document FPGA solutions.
Perform FPGA board bring-up, hardware debugging, and lab testing.
Conduct timing analysis and timing closure.
Support software and system integration/testing.
Participate in design reviews and technical documentation.
Required Skills
Strong VHDL/FPGA development experience.
Xilinx FPGA tools and architectures.
DSP, MATLAB modeling and simulation.
Linux development environment.
ModelSim/Questa experience.
FPGA hardware bring-up and debugging.
Timing analysis and closure.
Experience with RF, SDR, radar, or communications systems preferred.
Show more Show less
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