ML
Senior Faculty – Design Verification
Accepting applicationsMOSart Labs · Hyderabad, Telangana, India
Full-Time Mid_senior ASICAnalogCadenceDDREthernet
Estimated market salary
₹49-89 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
1d ago
Category
Verification
Experience
Mid_senior
Country
India
Senior Design Verification Faculty
Location: Hyderabad – Work From Office | Monday to Saturday | Full-Time
Reports To: Head – Academics / Training Delivery
About MOSart Labs
MOSart Labs is a leading Semiconductor Training & Chip Design company focused on building industry-ready VLSI engineers through hands-on, industry-focused training. Our programs include Design Verification, Physical Design, RTL Design, IIT Bhubaneswar PG Diploma and Zero to Silicon programs, with industry-tool exposure, projects and mentorship from semiconductor professionals.
Role
We are looking for an experienced Senior Design Verification Faculty with 5–10 years of semiconductor industry experience and a strong passion for teaching and mentoring.
This is a full-time teaching role responsible for delivering offline classroom training, hands-on labs, student mentoring, assessments, project guidance, and placement preparation in Design Verification and Advanced Design Verification.
Key Responsibilities
Deliver classroom training on Design Verification and Advanced Design Verification.
Conduct hands-on labs using SystemVerilog, UVM and industry-standard EDA tools.
Teach concepts through practical examples, live coding, simulation and debugging.
Guide mini-projects and industry-level verification projects from planning to verification closure.
Mentor students on technical concepts, projects, internships and placement preparation.
Develop and update course content, lecture materials, lab manuals, assignments, assessments and project statements.
Conduct technical evaluations, project reviews and doubt-clearing sessions.
Track student performance and provide technical guidance.
Stay updated with latest verification methodologies, protocols, tools and industry practices.
Collaborate with internal technical teams to continuously improve the curriculum.
Subject Expertise Required
Design Verification
SystemVerilog Fundamentals
Testbench Development
Constrained Random Verification
Functional & Code Coverage
SystemVerilog Assertions (SVA)
Scoreboards & Drivers
Verification Planning & Flow
Debugging & Regression
Industry EDA Tools
Verification Projects
Advanced Design Verification
UVM Methodology
Advanced Verification Techniques
Verification IP (VIP)
Protocol Verification
Coverage Closure
Assertion-Based Verification
Analog/Mixed-Signal Verification
SoC/IP Verification
Regression & Debugging
Industry Verification Projects
Protocol experience preferred: AXI/AXI4, AHB, APB, ACE/CHI, PCIe, DDR, Ethernet, USB, SPI, I2C, UART, and other SoC/IP protocols.
EDA Tool Experience
Hands-on experience with one or more:
Synopsys VCS / Verdi
Cadence Xcelium / SimVision
Siemens Questa / ModelSim
Other industry-standard verification tools
Scripting: Linux/Unix, Shell, TCL, Python; Perl is an added advantage.
Qualification
Mandatory
M.Tech / M.E. / M.S. in VLSI, Microelectronics, Electronics, Electrical Engineering or related specialization from IITs, NITs, IIITs, Central Universities or other reputed institutions.
Strong hands-on expertise in SystemVerilog and UVM.
Preferred
Ph.D. in VLSI, Semiconductor Engineering, Design Verification, or related field.
Prior Faculty / VLSI Trainer / Technical Trainer / Corporate Trainer / Mentor experience.
Experience with complex ASIC/IP/SoC verification projects and advanced protocols.
Experience
5–10 years of relevant industry experience in ASIC/IP/SoC Design Verification.
Strong practical experience in SystemVerilog and UVM-based verification.
Semiconductor industry experience is strongly preferred.
Prior teaching/training/mentoring experience is an added advantage.
Required Faculty Skills
Excellent communication and presentation skills.
Strong classroom management and mentoring abilities.
Passion for teaching and developing industry-ready VLSI engineers.
Ability to simplify complex technical concepts through practical demonstrations.
Ability to conduct interactive classroom and hands-on lab sessions.
Strong debugging, problem-solving and student-handling skills.
Ability to convert real-world industry experience into practical, project-oriented training.
What We Offer
Opportunity to work with a fast-growing Semiconductor Training & Chip Design organization.
Opportunity to train and mentor the next generation of Design Verification Engineers.
Exposure to industry-standard EDA tools, methodologies and real-world projects.
Competitive compensation based on experience and expertise.
Professional growth and technical leadership opportunities.
Collaborative and innovation-driven work environment.
If you are an experienced Design Verification professional who is passionate about teaching, mentoring, and building the next generation of VLSI engineers, we would like to hear from you
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Location: Hyderabad – Work From Office | Monday to Saturday | Full-Time
Reports To: Head – Academics / Training Delivery
About MOSart Labs
MOSart Labs is a leading Semiconductor Training & Chip Design company focused on building industry-ready VLSI engineers through hands-on, industry-focused training. Our programs include Design Verification, Physical Design, RTL Design, IIT Bhubaneswar PG Diploma and Zero to Silicon programs, with industry-tool exposure, projects and mentorship from semiconductor professionals.
Role
We are looking for an experienced Senior Design Verification Faculty with 5–10 years of semiconductor industry experience and a strong passion for teaching and mentoring.
This is a full-time teaching role responsible for delivering offline classroom training, hands-on labs, student mentoring, assessments, project guidance, and placement preparation in Design Verification and Advanced Design Verification.
Key Responsibilities
Deliver classroom training on Design Verification and Advanced Design Verification.
Conduct hands-on labs using SystemVerilog, UVM and industry-standard EDA tools.
Teach concepts through practical examples, live coding, simulation and debugging.
Guide mini-projects and industry-level verification projects from planning to verification closure.
Mentor students on technical concepts, projects, internships and placement preparation.
Develop and update course content, lecture materials, lab manuals, assignments, assessments and project statements.
Conduct technical evaluations, project reviews and doubt-clearing sessions.
Track student performance and provide technical guidance.
Stay updated with latest verification methodologies, protocols, tools and industry practices.
Collaborate with internal technical teams to continuously improve the curriculum.
Subject Expertise Required
Design Verification
SystemVerilog Fundamentals
Testbench Development
Constrained Random Verification
Functional & Code Coverage
SystemVerilog Assertions (SVA)
Scoreboards & Drivers
Verification Planning & Flow
Debugging & Regression
Industry EDA Tools
Verification Projects
Advanced Design Verification
UVM Methodology
Advanced Verification Techniques
Verification IP (VIP)
Protocol Verification
Coverage Closure
Assertion-Based Verification
Analog/Mixed-Signal Verification
SoC/IP Verification
Regression & Debugging
Industry Verification Projects
Protocol experience preferred: AXI/AXI4, AHB, APB, ACE/CHI, PCIe, DDR, Ethernet, USB, SPI, I2C, UART, and other SoC/IP protocols.
EDA Tool Experience
Hands-on experience with one or more:
Synopsys VCS / Verdi
Cadence Xcelium / SimVision
Siemens Questa / ModelSim
Other industry-standard verification tools
Scripting: Linux/Unix, Shell, TCL, Python; Perl is an added advantage.
Qualification
Mandatory
M.Tech / M.E. / M.S. in VLSI, Microelectronics, Electronics, Electrical Engineering or related specialization from IITs, NITs, IIITs, Central Universities or other reputed institutions.
Strong hands-on expertise in SystemVerilog and UVM.
Preferred
Ph.D. in VLSI, Semiconductor Engineering, Design Verification, or related field.
Prior Faculty / VLSI Trainer / Technical Trainer / Corporate Trainer / Mentor experience.
Experience with complex ASIC/IP/SoC verification projects and advanced protocols.
Experience
5–10 years of relevant industry experience in ASIC/IP/SoC Design Verification.
Strong practical experience in SystemVerilog and UVM-based verification.
Semiconductor industry experience is strongly preferred.
Prior teaching/training/mentoring experience is an added advantage.
Required Faculty Skills
Excellent communication and presentation skills.
Strong classroom management and mentoring abilities.
Passion for teaching and developing industry-ready VLSI engineers.
Ability to simplify complex technical concepts through practical demonstrations.
Ability to conduct interactive classroom and hands-on lab sessions.
Strong debugging, problem-solving and student-handling skills.
Ability to convert real-world industry experience into practical, project-oriented training.
What We Offer
Opportunity to work with a fast-growing Semiconductor Training & Chip Design organization.
Opportunity to train and mentor the next generation of Design Verification Engineers.
Exposure to industry-standard EDA tools, methodologies and real-world projects.
Competitive compensation based on experience and expertise.
Professional growth and technical leadership opportunities.
Collaborative and innovation-driven work environment.
If you are an experienced Design Verification professional who is passionate about teaching, mentoring, and building the next generation of VLSI engineers, we would like to hear from you
Show more Show less