R-
Senior Emulation Engineer
Accepting applicationsRapinnoTech - APAC & USA · San Jose, CA
Contract Mid_senior C++CadenceFPGAPCIePerl
Posted
3d ago
Category
Verification
Experience
Mid_senior
Country
United States
Senior Emulation Engineer
Location: San Jose, CA (Onsite but Remote also fine)
Exp: 10+ years
We are looking for a Senior Emulation Engineer with strong experience in SoC emulation, pre-silicon validation, and hardware/software bring-up.
Key Skills & Responsibilities:
Strong hands-on experience with Siemens Veloce, Cadence Palladium, or Synopsys ZeBu emulation platforms.
Experience setting up, configuring, maintaining, and optimizing emulation and FPGA-based prototyping environments.
Strong expertise in SoC design, RTL, Verilog/SystemVerilog, and digital design methodologies.
Hands-on experience emulating and validating high-speed interfaces such as PCIe and UCIe.
Experience with memory technologies including LPDDR and HBM.
Develop and debug emulation testbenches, system-level environments, and pre-silicon validation flows.
Experience supporting early software/firmware bring-up, OS and driver testing, and silicon bring-up activities.
Strong debugging skills using waveform viewers, logic analyzers, hardware debug tools, and emulation debug environments.
Proficiency in Python, Tcl, or Perl scripting for automation, regression, infrastructure, and performance optimization.
Experience with UVM, SystemVerilog-based verification, simulation/testbench environments; C/C++ software development experience is a plus.
Education: BS/MS/PhD in Electrical Engineering, Computer Science, or related field.
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Location: San Jose, CA (Onsite but Remote also fine)
Exp: 10+ years
We are looking for a Senior Emulation Engineer with strong experience in SoC emulation, pre-silicon validation, and hardware/software bring-up.
Key Skills & Responsibilities:
Strong hands-on experience with Siemens Veloce, Cadence Palladium, or Synopsys ZeBu emulation platforms.
Experience setting up, configuring, maintaining, and optimizing emulation and FPGA-based prototyping environments.
Strong expertise in SoC design, RTL, Verilog/SystemVerilog, and digital design methodologies.
Hands-on experience emulating and validating high-speed interfaces such as PCIe and UCIe.
Experience with memory technologies including LPDDR and HBM.
Develop and debug emulation testbenches, system-level environments, and pre-silicon validation flows.
Experience supporting early software/firmware bring-up, OS and driver testing, and silicon bring-up activities.
Strong debugging skills using waveform viewers, logic analyzers, hardware debug tools, and emulation debug environments.
Proficiency in Python, Tcl, or Perl scripting for automation, regression, infrastructure, and performance optimization.
Experience with UVM, SystemVerilog-based verification, simulation/testbench environments; C/C++ software development experience is a plus.
Education: BS/MS/PhD in Electrical Engineering, Computer Science, or related field.
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