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Senior DV Engineer – UVM/SystemVerilog (BB810ST RM 4328)
Accepting applicationsSource-Right · Bengaluru, Karnataka, India
Full-Time Senior SystemVerilogUVM
Estimated market salary
₹24-44 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
4d ago
Category
Verification
Experience
Senior
Country
India
Position: Senior DV Engineer – UVM/SystemVerilog (BB810ST RM 4328)
Very good knowledge of UVM and SystemVerilog.
Some networking experience/exposure is welcome.
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Very good knowledge of UVM and SystemVerilog.
Some networking experience/exposure is welcome.
Show more Show less