MT
Senior DSP Engineer
Accepting applicationsMulya Technologies · Greater Bengaluru Area
Full-Time Mid_senior AICadenceEthernetFPGAGenus
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
India
www.omnidesigntech.com
Bangalore
Company Description
We are a leading provider of high-performance, ultra-low power IP cores optimized for advanced semiconductor nodes, enabling the development of cutting-edge systems-on-chip (SoCs) for applications such as 5G, AI, LiDAR, radar, networking, and IoT. Known for its innovative small geometry solutions, our expertise encompasses data converter IP cores ranging from 6-bit to 14-bit resolutions and sampling rates up to over 20 Gsps.
Apart from the above we need 5+ year DSP engineers with Serdes background.
Senior DSP Engineer (5+ Years)
Core Expertise
DSP Algorithms for SerDes:
Deep knowledge of equalization (FFE/DFE), echo cancellation, adaptive filtering, CDR loops.
Experience across Ethernet, PCIe, UCIe high-speed serial links.
Skilled in channel modelling, jitter/noise analysis, BER optimization.
Digital RTL & FPGA Prototyping:
Strong background in RTL design and verification using Cadence digital tools (Knowledge wrt Genus for synthesis, Innovus for P&R, JasperGold for formal verification).
Hands-on FPGA prototyping of SerDes DSP blocks (Xilinx Vivado, Intel Quartus).
Implemented training sequence debug, retimer logic, and sideband channel handling on FPGA platforms.
Lab Debug & Validation:
Bench expertise with oscilloscopes, BERTs and high-speed probes.
Experience in silicon bring-up, validation, and correlation with simulation models.
Qualifications
Education: B.E./M.Tech in Electrical/Electronics Engineering (Signal processing specialization).
Experience: 5+ years in DSP algorithm development for SerDes PHYs.
Tools & Languages:
MATLAB, Python (algorithm modeling, post-processing).
Cadence digital RTL tools .
FPGA toolchains.
Soft Skills: Analytical problem-solving, cross-functional collaboration, clear technical communication.
Responsibilities
Develop and optimize DSP algorithms for SerDes PHYs (Ethernet/PCIe/UCIe).
Prototype DSP blocks on FPGA platforms for pre-silicon validation.
Perform lab debug and silicon characterization of high-speed links.
Collaborate with analog/mixed-signal teams on CDR, PLL/DLL, equalization schemes.
Document workflows and support IP integration into customer SoCs.
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
"Mining The Knowledge Community"
Show more Show less
Bangalore
Company Description
We are a leading provider of high-performance, ultra-low power IP cores optimized for advanced semiconductor nodes, enabling the development of cutting-edge systems-on-chip (SoCs) for applications such as 5G, AI, LiDAR, radar, networking, and IoT. Known for its innovative small geometry solutions, our expertise encompasses data converter IP cores ranging from 6-bit to 14-bit resolutions and sampling rates up to over 20 Gsps.
Apart from the above we need 5+ year DSP engineers with Serdes background.
Senior DSP Engineer (5+ Years)
Core Expertise
DSP Algorithms for SerDes:
Deep knowledge of equalization (FFE/DFE), echo cancellation, adaptive filtering, CDR loops.
Experience across Ethernet, PCIe, UCIe high-speed serial links.
Skilled in channel modelling, jitter/noise analysis, BER optimization.
Digital RTL & FPGA Prototyping:
Strong background in RTL design and verification using Cadence digital tools (Knowledge wrt Genus for synthesis, Innovus for P&R, JasperGold for formal verification).
Hands-on FPGA prototyping of SerDes DSP blocks (Xilinx Vivado, Intel Quartus).
Implemented training sequence debug, retimer logic, and sideband channel handling on FPGA platforms.
Lab Debug & Validation:
Bench expertise with oscilloscopes, BERTs and high-speed probes.
Experience in silicon bring-up, validation, and correlation with simulation models.
Qualifications
Education: B.E./M.Tech in Electrical/Electronics Engineering (Signal processing specialization).
Experience: 5+ years in DSP algorithm development for SerDes PHYs.
Tools & Languages:
MATLAB, Python (algorithm modeling, post-processing).
Cadence digital RTL tools .
FPGA toolchains.
Soft Skills: Analytical problem-solving, cross-functional collaboration, clear technical communication.
Responsibilities
Develop and optimize DSP algorithms for SerDes PHYs (Ethernet/PCIe/UCIe).
Prototype DSP blocks on FPGA platforms for pre-silicon validation.
Perform lab debug and silicon characterization of high-speed links.
Collaborate with analog/mixed-signal teams on CDR, PLL/DLL, equalization schemes.
Document workflows and support IP integration into customer SoCs.
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
"Mining The Knowledge Community"
Show more Show less