PD
Senior Director, Physical Design & Backend Engineering (HPC)
Accepting applicationsPrestige Development Group · Texas, United States
Full-Time Principal CadenceMentorRTLSoCSynopsys
Posted
6d ago
Category
Design
Experience
Principal
Country
United States
Job Title: Senior Director, Physical Design & Backend Engineering (HPC)
Location: On-Site/Austin,TX
Department: HPC Division
Reports To: HPC Hardware Engineering
Job Type: Full-Time About Prestige Development Group (PDG)
Prestige Development Group (PDG) specializes in providing innovative human capital management solutions tailored to meet the needs of both private and public sector organizations. We are a certified SBA HUBZone and Economically Disadvantaged Woman-Owned Small Business dedicated to fostering diversity, inclusion, and operational excellence. Position Summary
We are seeking a Senior Director to own end-to-end backend execution across its HPC SoC and MCU programs implementation, signoff, and convergence from RTL to GDSII. This is a backfill for the outgoing Senior Director and is currently one of the hiring manager s highest-priority open roles. The person leads a 350+ engineer organization spanning India, Japan, and Vietnam (5 6 direct reports), and is accountable for on-time, high-quality silicon delivery against defined power, performance, and area (PPA) targets across multiple concurrent programs. Key Responsibilities
Lead end-to-end physical design and backend implementation from RTL to GDSII, including signoff and tape-out.
Manage and mentor a global organization of 350+ engineers across multiple international locations.
Drive on-time delivery of concurrent SoC and MCU programs while meeting PPA, quality, and schedule targets.
Establish backend engineering strategy and optimize design methodologies for advanced-node products.
Partner with cross-functional and executive teams to ensure successful program execution and silicon delivery.
Qualifications
Required
Master s degree in Electrical Engineering, Computer Engineering, or related field.
15 18+ years leading physical design / backend implementation teams.
Proven, personal ownership of full-chip RTL-to-GDSII execution synthesis, P&R, timing closure (STA), physical verification, and signoff through tape-out.
Experience leading large, multi-site, globally distributed engineering organizations.
Working fluency with Cadence, Synopsys, and Mentor Graphics flows (directing teams, not necessarily hands-on daily use).
Track record of PPA accountability across concurrent SoC/MCU programs.
Preferred:
Automotive semiconductor background.
Direct exposure to advanced nodes (2 3nm).
Experience managing blended teams of FTEs and contractors across multiple geographies.
Compensation & Benefits
Salary Range: $260,000 $290,000 USD
Benefits: [Examples: Medical, dental, and vision insurance, paid time off, professional development opportunities, retirement savings plans, etc.]
Additional benefits and perks may be included based on the role.
Equal Employment Opportunity (EEO) Statement
Prestige Development Group (PDG) is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. PDG prohibits discrimination and harassment of any kind, including based on race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, disability, genetic information, or any other protected characteristic as outlined by federal, state, or local laws. Americans with Disabilities Act (ADA) Statement
PDG is committed to providing reasonable accommodations for individuals with disabilities in our job application and hiring process. Background Check Policy
Employment is contingent upon the successful completion of a background check. PDG complies with all applicable laws regarding background checks. How to Apply
Interested candidates are encouraged to submit their resume. Applications will be reviewed on a rolling basis until the position is filled.
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Location: On-Site/Austin,TX
Department: HPC Division
Reports To: HPC Hardware Engineering
Job Type: Full-Time About Prestige Development Group (PDG)
Prestige Development Group (PDG) specializes in providing innovative human capital management solutions tailored to meet the needs of both private and public sector organizations. We are a certified SBA HUBZone and Economically Disadvantaged Woman-Owned Small Business dedicated to fostering diversity, inclusion, and operational excellence. Position Summary
We are seeking a Senior Director to own end-to-end backend execution across its HPC SoC and MCU programs implementation, signoff, and convergence from RTL to GDSII. This is a backfill for the outgoing Senior Director and is currently one of the hiring manager s highest-priority open roles. The person leads a 350+ engineer organization spanning India, Japan, and Vietnam (5 6 direct reports), and is accountable for on-time, high-quality silicon delivery against defined power, performance, and area (PPA) targets across multiple concurrent programs. Key Responsibilities
Lead end-to-end physical design and backend implementation from RTL to GDSII, including signoff and tape-out.
Manage and mentor a global organization of 350+ engineers across multiple international locations.
Drive on-time delivery of concurrent SoC and MCU programs while meeting PPA, quality, and schedule targets.
Establish backend engineering strategy and optimize design methodologies for advanced-node products.
Partner with cross-functional and executive teams to ensure successful program execution and silicon delivery.
Qualifications
Required
Master s degree in Electrical Engineering, Computer Engineering, or related field.
15 18+ years leading physical design / backend implementation teams.
Proven, personal ownership of full-chip RTL-to-GDSII execution synthesis, P&R, timing closure (STA), physical verification, and signoff through tape-out.
Experience leading large, multi-site, globally distributed engineering organizations.
Working fluency with Cadence, Synopsys, and Mentor Graphics flows (directing teams, not necessarily hands-on daily use).
Track record of PPA accountability across concurrent SoC/MCU programs.
Preferred:
Automotive semiconductor background.
Direct exposure to advanced nodes (2 3nm).
Experience managing blended teams of FTEs and contractors across multiple geographies.
Compensation & Benefits
Salary Range: $260,000 $290,000 USD
Benefits: [Examples: Medical, dental, and vision insurance, paid time off, professional development opportunities, retirement savings plans, etc.]
Additional benefits and perks may be included based on the role.
Equal Employment Opportunity (EEO) Statement
Prestige Development Group (PDG) is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. PDG prohibits discrimination and harassment of any kind, including based on race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, disability, genetic information, or any other protected characteristic as outlined by federal, state, or local laws. Americans with Disabilities Act (ADA) Statement
PDG is committed to providing reasonable accommodations for individuals with disabilities in our job application and hiring process. Background Check Policy
Employment is contingent upon the successful completion of a background check. PDG complies with all applicable laws regarding background checks. How to Apply
Interested candidates are encouraged to submit their resume. Applications will be reviewed on a rolling basis until the position is filled.
Show more Show less