ED
Senior Director – DFT_Visakhapatnam
Accepting applicationsEximietas Design · Hyderabad, Telangana, India
Full-Time Principal ATPGAnalogBoundary ScanCadenceDFT
Estimated market salary
₹40-72 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
4d ago
Category
Test
Experience
Principal
Country
India
Hi All,
Greetings from Eximietas Design...!
🚀 We're Hiring | Senior DFT Director | Eximietas Design
📍Locations:
India: Bengaluru, Hyderabad, Ahmedabad & Visakhapatnam.
📍San Jose (Bay Area), USA
Eligibility (USA): U.S. Permanent Residents (Green Card holders).
💼 Experience: Min 25+ Years
Job Description:
We are seeking motivated Design for Test (DFT) professionals to join our growing team. You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across complex IP, Subsystem, and SoC designs.
Key Skills:
✔ End-to-End DFT Flow Ownership.
✔ Scan Insertion, EDT & OCC.
✔ ATPG, DRC Analysis & Coverage Closure.
✔ Pattern Simulation & Debugging.
✔ SoC Integration & Pattern Retargeting.
✔ MBIST, IJTAG & JTAG Implementation.
✔ DFT Sign-off Activities.
Tools Expertise:
🔹 Siemens Tessent.
🔹 Synopsys TestMAX / TetraMAX.
🔹 Cadence Modus.
Preferred Skills:
✅ Streaming Scan Network (SSN).
✅ Analog & Mixed-Signal DFT.
✅ SpyGlass DFT.
✅ RTL DFT Methodologies.
✅ TCL, Python & Perl Scripting.
Core Responsibilities:
• End-to-end ownership of DFT implementation flow from RTL to sign-off.
• Scan architecture implementation including EDT & OCC.
• ATPG, DRC analysis, coverage optimization, and pattern simulations.
• SoC integration, pattern retargeting, and DFT debugging.
• MBIST, IJTAG, and Boundary Scan (JTAG) integration.
• Collaboration with Design, Verification, and Physical Design teams.
• DFT sign-off ownership and deliverables.
Technical Requirements:
• Strong experience in ATPG simulations and netlist handling.
• Expertise in block-level and SoC-level pattern retargeting/debugging.
• Strong understanding of ICL and PDL standards.
• Hands-on experience with Tessent, TestMAX/TetraMAX, or Modus.
📩 Interested candidates can share their updated resume at: maruthiprasad.e@eximietas.design
📞 Contact: +91 8088969910
🤝 Referrals are highly appreciated. Please share within your network.
Best Regards,
Maruthy Prasaad
Associate VLSI Manager – Talent Acquisition | Visakhapatnam
Eximietas Design (Excellence by Design)
Inspired by nature, driven by silicon.
Show more Show less
Greetings from Eximietas Design...!
🚀 We're Hiring | Senior DFT Director | Eximietas Design
📍Locations:
India: Bengaluru, Hyderabad, Ahmedabad & Visakhapatnam.
📍San Jose (Bay Area), USA
Eligibility (USA): U.S. Permanent Residents (Green Card holders).
💼 Experience: Min 25+ Years
Job Description:
We are seeking motivated Design for Test (DFT) professionals to join our growing team. You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across complex IP, Subsystem, and SoC designs.
Key Skills:
✔ End-to-End DFT Flow Ownership.
✔ Scan Insertion, EDT & OCC.
✔ ATPG, DRC Analysis & Coverage Closure.
✔ Pattern Simulation & Debugging.
✔ SoC Integration & Pattern Retargeting.
✔ MBIST, IJTAG & JTAG Implementation.
✔ DFT Sign-off Activities.
Tools Expertise:
🔹 Siemens Tessent.
🔹 Synopsys TestMAX / TetraMAX.
🔹 Cadence Modus.
Preferred Skills:
✅ Streaming Scan Network (SSN).
✅ Analog & Mixed-Signal DFT.
✅ SpyGlass DFT.
✅ RTL DFT Methodologies.
✅ TCL, Python & Perl Scripting.
Core Responsibilities:
• End-to-end ownership of DFT implementation flow from RTL to sign-off.
• Scan architecture implementation including EDT & OCC.
• ATPG, DRC analysis, coverage optimization, and pattern simulations.
• SoC integration, pattern retargeting, and DFT debugging.
• MBIST, IJTAG, and Boundary Scan (JTAG) integration.
• Collaboration with Design, Verification, and Physical Design teams.
• DFT sign-off ownership and deliverables.
Technical Requirements:
• Strong experience in ATPG simulations and netlist handling.
• Expertise in block-level and SoC-level pattern retargeting/debugging.
• Strong understanding of ICL and PDL standards.
• Hands-on experience with Tessent, TestMAX/TetraMAX, or Modus.
📩 Interested candidates can share their updated resume at: maruthiprasad.e@eximietas.design
📞 Contact: +91 8088969910
🤝 Referrals are highly appreciated. Please share within your network.
Best Regards,
Maruthy Prasaad
Associate VLSI Manager – Talent Acquisition | Visakhapatnam
Eximietas Design (Excellence by Design)
Inspired by nature, driven by silicon.
Show more Show less