Senior Digital Verification Engineer

We are hiring for a Senior Digital Verification Engineer in Pittsford, New York.

This is a hybrid position.

Responsibilities
The digital verification engineer shall read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects.
You are held responsible for the complete and detailed validation of one or more architectural functional blocks by using an appropriate combination of simulation, formal and coverage methods.
You will contribute to verification planning, functional coverage definition and possibly formal verification test plans.
You are accountable for the creation or integration of the test bench environment(s) and/or components, agents, scoreboard, and all test scenarios related to your architectural functional block using System Verilog UVM and/or C where applicable.
You will perform coverage-driven verification, monitor regressions and debug resulting failures with the help of the function's designer.


Required Skills
Electrical or computer engineering, computer science or other applicable completed scientific degree at the BEng/BSc, MEng/MSc or higher level
Proficiency above the intermediate level with the use of System Verilog, UVM, SVA, and simulators from major vendors.
A highly motivated self-starter, able to work independently, while being a great teammate
Experience with formal verification methods
Experience with standards and protocols such as OTN/FlexO/B100G, Ethernet (100GE+)
Experience with using GIT for source code management and revision tracking
Experience with using Jira for schedule planning, assignment tracking and bug reporting
Familiarity with programming languages such as Python, Make, bash, object-oriented programming, C, C++, System C


Please apply with your updated resume.
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