Senior Digital Verification Engineer

We are hiring experienced Digital Verification Engineers to own the functional verification of complex SoC/ASIC designs from testbench architecture through coverage closure and sign-off.

What you'll do
Architect and build UVM/SystemVerilog testbenches for block- and SoC-level verification
Develop verification plans, drive coverage closure (functional + code), and own sign-off quality
Write SVA assertions and constraints, debug complex failures, and collaborate with design and DFT teams
Contribute to methodology, reuse, and regression infrastructure.

What we're looking for
5+ years of hands-on digital/functional verification experience (block and/or SoC level)
Strong SystemVerilog and UVM; solid grasp of SVA, constrained-random, and coverage-driven verification
Experience with industry simulators (Xcelium / VCS / Questa) and debug flows
Proven track record across at least one tape-out
Clear communicator who can work independently and own deliverables

Location & eligibility
US-based candidates only. You must currently reside in the United States and be authorized to work in the US without sponsorship.

To apply: Send your resume to avddhesh@andgatetech.com.

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