SI
Senior DFT Engineer (TestMAX)
Accepting applicationsSynopsys Inc · Bengaluru, Karnataka, India
Full-Time Mid_senior AIATPGC++DFTRTL
Estimated market salary
₹24-43 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
4d ago
Category
Test
Experience
Mid_senior
Country
India
Synopsys is looking for a Senior Staff R&D Engineer to join our advanced DFT team and contribute to the evolution of our Streaming Fabric (SF) and SEQ technologies within the TestMAX product family. Does this sound like a good role for you?
Senior Staff DFT Engineer (R&D Engineering)
Location: Bangalore
Experience: 3yrs to 10yrs
BE/BTECH/Master’s degree in Electronics, Computer Science, or equivalent
3 years of hands-on experience in the DFT domain
Strong understanding of DFT, scan architectures, and test‑generation concepts
Hands‑on experience with Verilog and logic‑simulation debug
Proficiency in C/C++ programming
Openness to using AI tools to boost productivity
Responsibilities:
Contribute across the entire DFT flow: RTL, netlist, ATPG, and logic simulation
Analyze DFT IP behavior, debug logic issues, and deliver robust fixes
Enhance pattern‑generation workflows for better performance and QoR
Develop C/C++ components for pattern processing, automation, and data handling
Work closely with multi‑site R&D teams to ensure smooth flow integration
Use AI‑based tools to accelerate debugging, code comprehension, and analysis
Please share your updated CV with taufiq@synopsys.com or refer those who would like to explore this opportunity.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.
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Senior Staff DFT Engineer (R&D Engineering)
Location: Bangalore
Experience: 3yrs to 10yrs
BE/BTECH/Master’s degree in Electronics, Computer Science, or equivalent
3 years of hands-on experience in the DFT domain
Strong understanding of DFT, scan architectures, and test‑generation concepts
Hands‑on experience with Verilog and logic‑simulation debug
Proficiency in C/C++ programming
Openness to using AI tools to boost productivity
Responsibilities:
Contribute across the entire DFT flow: RTL, netlist, ATPG, and logic simulation
Analyze DFT IP behavior, debug logic issues, and deliver robust fixes
Enhance pattern‑generation workflows for better performance and QoR
Develop C/C++ components for pattern processing, automation, and data handling
Work closely with multi‑site R&D teams to ensure smooth flow integration
Use AI‑based tools to accelerate debugging, code comprehension, and analysis
Please share your updated CV with taufiq@synopsys.com or refer those who would like to explore this opportunity.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.
Show more Show less