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Senior DFT Engineer - LPU
Accepting applicationsLadders · United States
Full-Time Mid_senior AIASICATPGDFTJTAG
Posted
1d ago
Category
Test
Experience
Mid_senior
Country
United States
For our client, we are seeking a Senior DFT Engineer - LPU to join the team of a leader in the Telecommunications & Hardware space. This role will lead work at the intersection of data, AI-enabled capabilities, and scalable technology delivery. You will work across engineering, product, operations, and business stakeholders to translate complex requirements into practical technology solutions. The position offers the opportunity to influence architecture, execution quality, and the technology capabilities that enable long-term growth within a Telecommunications & Hardware environment.
Location: Remote - US based candidates only, no visa sponsorship available
Compensation: $136,000 – $264,500 annually
Responsibilities
Define and implement SCAN, MBIST, and JTAG debug structures for post-Si testing plans
Drive the creation of ATPG and MBIST test vectors for DFT
Build DFT timing constraints and collaborate with Physical Design and STA sign-off teams
Work with the post-silicon team to bring up test patterns on silicon
Collaborate with the CAD methodology team to introduce AI-driven optimizations in DFT
Qualifications
Bachelor's or M.S. in Computer Engineering or Electrical Engineering (or equivalent experience) with 5+ years in DFT for high-performance ASICs
Practical experience with SCAN/MBIST/Test generation tools for large SoC/ASIC
Domain expertise in DFT techniques such as ATPG, test pattern translation, yield learning, and scan compression
Familiarity with ATPG Streaming SCAN Network (SSN) implementation
Consistent track record in yield estimation and test optimization
Excellent coding skills in Tcl and Python
Benefits
Comprehensive benefits package for employees and families
Equity options available for eligible employees
Diverse and supportive work environment encouraging innovation
Our client is an equal opportunity employer. We encourage you to apply even if you don’t meet every qualification—your background could be exactly what this team needs.
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Location: Remote - US based candidates only, no visa sponsorship available
Compensation: $136,000 – $264,500 annually
Responsibilities
Define and implement SCAN, MBIST, and JTAG debug structures for post-Si testing plans
Drive the creation of ATPG and MBIST test vectors for DFT
Build DFT timing constraints and collaborate with Physical Design and STA sign-off teams
Work with the post-silicon team to bring up test patterns on silicon
Collaborate with the CAD methodology team to introduce AI-driven optimizations in DFT
Qualifications
Bachelor's or M.S. in Computer Engineering or Electrical Engineering (or equivalent experience) with 5+ years in DFT for high-performance ASICs
Practical experience with SCAN/MBIST/Test generation tools for large SoC/ASIC
Domain expertise in DFT techniques such as ATPG, test pattern translation, yield learning, and scan compression
Familiarity with ATPG Streaming SCAN Network (SSN) implementation
Consistent track record in yield estimation and test optimization
Excellent coding skills in Tcl and Python
Benefits
Comprehensive benefits package for employees and families
Equity options available for eligible employees
Diverse and supportive work environment encouraging innovation
Our client is an equal opportunity employer. We encourage you to apply even if you don’t meet every qualification—your background could be exactly what this team needs.
Show more Show less