WA
Senior DFT engineer
Accepting applicationsWeekday AI (YC W21) · Bengaluru, Karnataka, India
Full-Time Associate DFTATPGMBISTScanJTAG
Estimated market salary
₹44-79 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
1d ago
Category
Test
Experience
Associate
Country
India
This role is for one of the Weekday's clients
Salary range: Rs 2400000 - Rs 7000000 (ie INR 24-70 LPA)
Experience: 5+ yrs
Location: Bengaluru
Job Type: Full-Time
We are seeking an experienced Senior DFT Engineer / Lead DFT Engineer to drive Design-for-Test (DFT) architecture, implementation, and silicon validation for complex SoC and ASIC designs. The ideal candidate will have strong expertise in scan architecture, ATPG, MBIST/LBIST, JTAG, DFT verification, and test pattern generation across advanced semiconductor technologies.
In this role, you will be responsible for developing robust DFT solutions that ensure high manufacturing test coverage, optimize test quality, and support successful silicon bring-up. You will collaborate closely with RTL, Physical Design, Verification, and Product Engineering teams to deliver high-quality, production-ready designs while mentoring junior engineers and contributing to DFT methodology improvements.
Requirements
Key Responsibilities
Design, implement, and validate DFT architecture for complex SoC and ASIC designs
Drive Scan Insertion, ATPG, Scan Compression, Pattern Retargeting, and Test Coverage optimization
Implement and verify JTAG, Boundary Scan, MBIST, LBIST, and other embedded test structures
Develop and maintain DFT constraints, test methodologies, and reusable DFT flows
Perform DFT verification using industry-standard simulation tools and debug scan-related issues
Generate production-quality ATPG patterns and coordinate with ATE teams for manufacturing test implementation
Analyze test coverage reports and identify opportunities to improve fault coverage while minimizing test time
Support post-silicon bring-up, diagnosis, yield improvement, and failure analysis activities
Collaborate with RTL, Physical Design, STA, and Verification teams to resolve DFT-related implementation challenges
Ensure compliance with DFT sign-off requirements, quality standards, and tape-out milestones
Mentor junior engineers, conduct technical reviews, and drive continuous improvements in DFT methodologies and best practices
What Makes You a Great Fit
5+ years of hands-on experience in Design-for-Test (DFT) for ASIC or SoC development
Strong expertise in Scan Insertion, ATPG, Scan Compression, Pattern Retargeting, and Test Coverage analysis
Proven experience with JTAG, Boundary Scan, MBIST, LBIST, and DFT logic integration
Hands-on experience with industry-standard DFT tools such as Tessent, Synopsys TestMAX, Modus, or equivalent
Strong understanding of digital design fundamentals, Verilog/SystemVerilog, and RTL-to-GDSII design flow
Experience debugging DFT issues during simulation, silicon validation, and manufacturing test
Familiarity with Gate-Level Simulation (GLS), timing verification, and post-silicon debug
Knowledge of advanced technology nodes and low-power design considerations is an advantage
Experience working closely with Physical Design, Verification, Product Engineering, and ATE teams
Strong scripting skills using Tcl, Perl, Python, or Shell for automation and productivity improvements
Excellent analytical, debugging, and problem-solving skills with attention to detail
Strong communication, leadership, and stakeholder management abilities with the capability to mentor engineering teams
Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related discipline
Show more Show less
Salary range: Rs 2400000 - Rs 7000000 (ie INR 24-70 LPA)
Experience: 5+ yrs
Location: Bengaluru
Job Type: Full-Time
We are seeking an experienced Senior DFT Engineer / Lead DFT Engineer to drive Design-for-Test (DFT) architecture, implementation, and silicon validation for complex SoC and ASIC designs. The ideal candidate will have strong expertise in scan architecture, ATPG, MBIST/LBIST, JTAG, DFT verification, and test pattern generation across advanced semiconductor technologies.
In this role, you will be responsible for developing robust DFT solutions that ensure high manufacturing test coverage, optimize test quality, and support successful silicon bring-up. You will collaborate closely with RTL, Physical Design, Verification, and Product Engineering teams to deliver high-quality, production-ready designs while mentoring junior engineers and contributing to DFT methodology improvements.
Requirements
Key Responsibilities
Design, implement, and validate DFT architecture for complex SoC and ASIC designs
Drive Scan Insertion, ATPG, Scan Compression, Pattern Retargeting, and Test Coverage optimization
Implement and verify JTAG, Boundary Scan, MBIST, LBIST, and other embedded test structures
Develop and maintain DFT constraints, test methodologies, and reusable DFT flows
Perform DFT verification using industry-standard simulation tools and debug scan-related issues
Generate production-quality ATPG patterns and coordinate with ATE teams for manufacturing test implementation
Analyze test coverage reports and identify opportunities to improve fault coverage while minimizing test time
Support post-silicon bring-up, diagnosis, yield improvement, and failure analysis activities
Collaborate with RTL, Physical Design, STA, and Verification teams to resolve DFT-related implementation challenges
Ensure compliance with DFT sign-off requirements, quality standards, and tape-out milestones
Mentor junior engineers, conduct technical reviews, and drive continuous improvements in DFT methodologies and best practices
What Makes You a Great Fit
5+ years of hands-on experience in Design-for-Test (DFT) for ASIC or SoC development
Strong expertise in Scan Insertion, ATPG, Scan Compression, Pattern Retargeting, and Test Coverage analysis
Proven experience with JTAG, Boundary Scan, MBIST, LBIST, and DFT logic integration
Hands-on experience with industry-standard DFT tools such as Tessent, Synopsys TestMAX, Modus, or equivalent
Strong understanding of digital design fundamentals, Verilog/SystemVerilog, and RTL-to-GDSII design flow
Experience debugging DFT issues during simulation, silicon validation, and manufacturing test
Familiarity with Gate-Level Simulation (GLS), timing verification, and post-silicon debug
Knowledge of advanced technology nodes and low-power design considerations is an advantage
Experience working closely with Physical Design, Verification, Product Engineering, and ATE teams
Strong scripting skills using Tcl, Perl, Python, or Shell for automation and productivity improvements
Excellent analytical, debugging, and problem-solving skills with attention to detail
Strong communication, leadership, and stakeholder management abilities with the capability to mentor engineering teams
Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related discipline
Show more Show less