CT
Senior DFT Engineer
Accepting applicationsChiplogic Technologies · Bengaluru, Karnataka, India
Full-Time Mid_senior AIATPGBISTDFTRTL
Estimated market salary
₹44-79 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
2d ago
Category
Test
Experience
Mid_senior
Country
India
Company Description Chiplogic Technologies (Chiplogic) is an IP and product engineering services company founded in 2018, specializing in Semiconductor, Systems, IoT, and AI/ML domains. The organization delivers high-quality, dependable engineering services, supporting customers across the full semiconductor design lifecycle. Chiplogic provides offshore development centers (ODC) and full turnkey design and system solutions, from concept to silicon. The company also offers proof-of-concept (POC) development and IoT system solutions, leveraging its VISARD™ (Video Synthesis And Real-time Dynamics) framework for advanced AI/ML applications.
Role Description The Senior DFT Engineer role is a full-time, on-site position based in Bengaluru. This role involves owning and executing Design-for-Test strategies for complex semiconductor designs, including scan insertion, ATPG, BIST, boundary scan, and test compression methodologies. The Senior DFT Engineer will collaborate closely with front-end and back-end design teams to integrate DFT features, define test requirements, and ensure testability without impacting performance or area targets. Typical responsibilities include developing and reviewing test plans, guiding test case creation, supporting test program development, analysing test results, and driving defect root-cause and yield improvement activities. The role also includes mentoring junior engineers, contributing to best practices, and engaging with customers on DFT solutions and implementation details.
Qualifications
Key requirements:
Strong hands-on experience with Siemens Tessent tools
Expertise in ICL and PDL development and validation
Experience in RTL and gate-level DFT verification
Strong understanding of DFT methodologies and pattern validation
Knowledge of post-silicon pattern handoff is preferred
Experience: 5–10 years
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Role Description The Senior DFT Engineer role is a full-time, on-site position based in Bengaluru. This role involves owning and executing Design-for-Test strategies for complex semiconductor designs, including scan insertion, ATPG, BIST, boundary scan, and test compression methodologies. The Senior DFT Engineer will collaborate closely with front-end and back-end design teams to integrate DFT features, define test requirements, and ensure testability without impacting performance or area targets. Typical responsibilities include developing and reviewing test plans, guiding test case creation, supporting test program development, analysing test results, and driving defect root-cause and yield improvement activities. The role also includes mentoring junior engineers, contributing to best practices, and engaging with customers on DFT solutions and implementation details.
Qualifications
Key requirements:
Strong hands-on experience with Siemens Tessent tools
Expertise in ICL and PDL development and validation
Experience in RTL and gate-level DFT verification
Strong understanding of DFT methodologies and pattern validation
Knowledge of post-silicon pattern handoff is preferred
Experience: 5–10 years
Show more Show less